AC/DC: An adaptive data cache prefetcher

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2004, Pages 135-145

  Nesbit, Kyle J ^a   Dhodapkar, Ashutosh S ^a   Smith, James E ^a  

^a Wisconsin Electric Machines and Power Electronics Consortium   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

GLOBAL HISTORY TABLE (GHT); PATTERN HISTORY TABLE (PGT); STRIDE PREFETCHING; TUNING ALGORITHM;

ALGORITHMS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER PROGRAMMING; MARKOV PROCESSES; PERSONAL COMPUTERS;

BUFFER STORAGE;

EID: 10444284911     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (27)

1. R. Bahar, and S. Manne, "Power and energy reduction via pipeline balancing," in Proc. of the 28th Ann. Intl. Symp. on Computer Architecture, pp. 218-229, Jul. 2001.
2. R. Balasubramonian, D. H. Albonesi, A. Buyuktosunoglu, and S. Dwarkadas, "Memory hierarchy reconfiguration for energy and performance in general purpose architectures," in Proc. of the 33rd Ann. Intl. Symp. on Microarchitecture, pp. 245-257, Dec. 2000.
3. D. Burger and T. Austin, "The SimpleScalar Toolset, Version 3.0.," http://www.simplescalar.org.
4. J. F. Cantin and M. D. Hill. Cache, "Performance for Selected SPEC CPU2000 Benchmarks," Oct. 2001. http://www.cs.wisc.edu/multifacet/misc/spec2000cachedata/
5. M. J. Charney and T. R. Puzak, "Prefetching and memory system behavior of the SPEC95 benchmark suite," IBM Journal of Research and Development, 31(3), 1997.
6. T. Chen and J. Baer, "Effective hardware based data prefetching for high-performance processors," IEEE Transactions on Computers, 44(5), pp. 609-623, May 1995.
7. V. Cuppu, B. Jacob, B. Davis, and T. Mudge, "Highperformance DRAMS in workstation environments," IEEE Transactions on Computers, 50(11), pp. 1133-1153, Nov. 2001.
8. A. S. Dhodapkar and J. E. Smith, "Managing Multi-Configuration Hardware via Dynamic Working Set Analysis," In Proc. of the 29th Ann. Intl. Symp. on Computer Architecture, pp. 233-245, May 2002.
9. J. W. C. Fu and J. H. Patel, "Stride directed prefetching in scalar processors," In Proc. of the 25th Ann. Symp. on Microarchitecture, pp. 102-110, Nov. 1992.
10. Z. Hu, M. Martonosi, S. Kaxiras, "TCP Tag Correlating Prefetchers," In Proc. of the 9th Ann. Intl. Symp. on High Performance Computer Architecture, pp. 317-326, Feb. 2003.
11. M. Huang, J. Renau, and J. Torrellas, "Positional adaptation of processors: application to energy reduction," in Proc. of the 30th Ann. Intl. Symp. on Computer Architecture, pp. 157-168, Jun. 2003.
12. D. Joseph and D. Grunwald, "Prefetching Using Markov Predictors," IEEE Transactions on Computers, 48(2), pp. 121-133, 1999.
13. N. Jouppi, "Improving direct-mapped cache performance by addition of a small fully associative cache and prefetch buffers," In Proc. of the 17th Intl. Symp. on Computer Architecture, pp. 364-373, June 1990.
14. T. Juan, S. Sanjeevan, and J. Navarro, "Dynamic history-length fitting: a third level of adaptivity for branch prediction," in Proc. of the 25th Ann. Intl. Symp. on Computer Architecture, pp. 155-166, June 1998.
15. G. Kandiraju and A. Sivasubramaniam, "Going the distance for TLB Prefetching: an application-driven study," In Proc. of the 29th Ann. Intl. Symp. on Computer Architecture, pp. 195-206, May 2002.
16. S. Kim and A. Veidenbaum, "Stride-directed prefetching for secondary caches," In Proc. of the 1997 Intl. Conf. on Parallel Processing, pp. 314-321, Aug. 1997.
17. A. Lai, C. Fide, and B. Falsafi, "Dead-block prediction and dead-block correlating prefetches," In Proc. of the 28th Ann. Intl. Symp. on Computer Architecture, pp. 144-154, July 2001.
18. K. Nesbit, and J. E. Smith, "Prefetching with a global history buffer," In Proc. of the 10th Ann.l Intl. Symp. on High Performance Computer Architecture, pp. 96-105, Feb. 2004.
19. S. Palacharla and R. Kessler, "Evaluating stream buffers as a secondary cache replacement," In Proc. of the 21st Ann. Intl. Symp. on Computer Architecture, pp. 24-33, May 1994.
20. Daniel Gracia Pérez, Gilles Mouchard, and Olivier Temam, "MicroLib: a case for the quantitative comparison of micro-architecture mechanisms", Workshop on Duplicating, Deconstructing, and Debunking, Munich Germany, June 2004.
21. T. Sherwood, S. Sair, and B. Calder, "Phase tracking and prediction," in Proc. of the 30th Ann. Intl. Symp. on Computer Architecture, pp. 336-347, Jun. 2003.
22. A. J. Smith, "Sequential program prefetching in memory hierarchies," IEEE Computer, 11(12), pp. 7-21, Dec. 1978.
23. J. E. Smith, and A. S. Dhodapkar, "Dynamic microarchitecture adaptation via co-designed virtual machines," in 2002 Intl. Solid State Circuits Conf., pp. 198-199, Feb. 2002.
24. Y. Solihin, J. Lee, and J. Torrellas, "Using a user-level memory thread for correlation prefetching," In Proc. of the 29th Ann. Intl. Symp. on Computer Architecture, pp. 171-182, May 2002.
25. J. M. Tendler, S. Dodson, S. Fields, H. Le, and B. Sinharoy, "POWER4 system microarchitecture," IBM Technical White Paper, 2001.
26. S. VanderWiel and D. Lilja, "Data prefetch mechanisms," ACM Computing Surveys, 32(2), pp. 174-199, June 1999.
27. Z. Wang, D. Burger, K. McKinley, S. Reinhardt, C. Weems, "Guided region prefetching: a cooperative hardware/software approach," In Proc. of the 30th Ann. Intl. Symp. on Computer Architecture, pp. 388-398, June 2003.