Effective stream-based and execution-based data prefetching

Proceedings of the International Conference on Supercomputing

Volumn , Issue , 2004, Pages 1-11

  Iacobovici, Sorin ^a   Spracklen, Lawrence ^a   Kadambi, Sudarshan ^a   Chou, Yuan ^a   Abraham, Santosh G ^a  

^a SUN MICROSYSTEMS   (United States)

Author keywords

Hardware prefetcher; Multiple strides; Stream prefetching

Indexed keywords

COMPUTER HARDWARE; COMPUTER SOFTWARE; DATA STORAGE EQUIPMENT; DATA STRUCTURES; PERFORMANCE; PROGRAM COMPILERS;

HARDWARE PREFETCHERS; MULTIPLE STRIDES; STREAM PREFETCHING; SUBSYSTEMS;

DATA PROCESSING;

EID: 8344236686     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1006209.1006211     Document Type: Conference Paper

References (31)

1. M. S. Lam, T. Mowry, and A. Gupta, "Design and evaluation of a compiler algorithm for prefetching," in Proceedings of the Fifth International Conference on Architectural Support for Programming Languages and Operating Systems, 1992, pp. 62-73.
2. P. Tirumalai et al., "Processor aware anticipatory prefetching in loops" in Proceedings of 10th International Symposium on High Performance Computer Architecture, 2004, pp. 106-118.
3. Advanced Micro Devices, Software Optimization Guide for AMD Athlon 64 and AMD Opteron Processors, 2003.
4. Intel Corporation, Intel Pentium 4 and Intel Xeon Processor Optimization, 2001.
5. S. Fields, H. Le, J. M. Tendler, S. Dodson, and B. Sinharoy, "POWER4 system microarchitecture," Technical white paper, 2001.
6. Sun Microsystems, UltraSPARC IIIcu user's manual, 2004.
7. T. Maruyama, "SPARC64 VI: Fujitsu's next generation processor," in Proceedings of the Microprocessor Forum, 2003.
8. Y. Jegou and O. Temem, "Speculative prefetching," in Proceedings of the International Conference on Supercomputing, 1992, pp. 1-11.
9. M. J. Charney and T. R. Puzak, "Prefetching and memory system behavior of the SPEC95 benchmark suite," IBM Journal of Research and Development, vol. 41, pp. 265-286, 1997.
10. N. P. Jouppi, "Improving direct-mapped cache performance by the addition of a small fully-associative cache prefetch buffers," in Proceedings of the 17th International Symposium on Computer Architecture, 1990, pp. 364-373.
11. S. Palacharla and R. E. Kessler, "Evaluating stream buffers as a secondary cache replacement," in Proceedings of the 21th International Symposium on Computer Architecture, 1994, pp. 24-33.
12. R. J. Eickemeyer and S. Vassiliadis, "A load instruction unit for pipelined processors," IBM Journal of Research and Development, Vol. 37, pp. 547-564, 1993.
13. C. Zhang and S. A. McKee, "Hardware-only stream prefetching and dynamic access ordering," in Proceedings of the 14th International Conference on Supercomputing, 2000, pp. 167-175.
14. N. Jouppi, K. Farkas, P. Chow, and Z. Vranesic, "Memory-system design considerations for dynamically-scheduled processors," in Proceedings of the 24th Annual International Symposium on Computer Architecture, 1997, pp. 133-143.
15. J. W. C. Fu, J. H. Patel, and B. L. Janssens "Stride directed prefetching in scalar processors," in Proceedings of the 25th Annual International Symposium on Computer Architecture, 1992, pp. 102-110.
16. N. D. Jouppi, K. Farkas, and P. Chow, "How useful are nonblocking loads, stream buffers, and speculative execution in multiple issue processors?," in Proceedings of the 1st International Symposium on High Performance Computer Architecture, 1995, pp. 78-89.
17. M. Dubois, F. Dahlgren, and P. Stenstrom, "Sequential hardware prefetching in shared-memory multiprocessors," IEEE Transactions on Parallel and Distributed Systems, vol. 6, pp. 733-764, 1995.
18. V. Srinivasan, E. S. Davidson, and G. S. Tyson, "A prefetch taxonomy," IEEE Transactions on Computers, vol. 53, pp. 126-140, 2004.
19. S. Sair, T. Sherwood, and B. Calder, "Predictor-directed stream buffers," in International Symposium on Microarchitecture, 2000, pp. 42-53.
20. D. Joseph and D. Grunwald, "Prefetching using Markov predictors," IEEE Transactions on Computers, vol. 48, no. 2, pp. 121-133, 1999.
21. A. Lai et al., "Dead-block prediction and dead-block correlating prefetchers," in the 28th Annual International Symposium on Computer Architecture, 2001, pp. 52-62.
22. Z. Hu, M. Martonosi, and S. Kaxiras, "TCP: Tag correlating prefetchers," in 9th International Symposium on High-Performance Computer Architecture, 2003, pp. 317-327.
23. J. L. Baer and T-F. Chen, "An effective on-chip preloading scheme to reduce data access penalty," in Proceedings of the 1991 ACM/IEEE conference on Supercomputing, 1991, pp. 176-186.
24. T-F. Chen and J-L. Baer, "Effective hardware-based data prefetching for high performance processors," in IEEE Transactions on Computers, 1995, pp. 609-623.
25. J. Dundas and T. N. Mudge, "Improving data cache performance by pre-executing instructions under a cache miss," in International Conference on Supercomputing, 1997, pp. 68-75.
26. O. Mutlu et al., "Runahead execution: An alternative to very large instruction windows for out-of-order processors," in 9th International Symposium on High-Performance Computer Architecture, 2003, pp. 129-141.
27. D. Kim and D. Yeung, "Design and evaluation of compiler algorithms for preexecution," in Proceedings of the Tenth International Conference on Architectural Support for Programming Languages and Operating Systems, 2002.
28. H. Wang, G. Hoflehner, D. Lavery, S. Liao, P. Wang, and J. Shen, "Post-pass binary adaptation for software-based speculative precomputation," in Proceedings of the ACM SIGPLAN 2002 Conference on Programming Language Design and Implementation, 2002, pp. 117-128.
29. A. Roth, A. Moshovos, and G. S. Sohi, "Dependence based prefetching for linked data structures," in 8th International Conference on Architectural Support for Programming Languages and Operating Systems, 1998, pp. 115-126.
30. K. Nesbit and J. Smith, "Neighborhood prefetching on multiprocessors using instruction history," in Proceedings of 10th International Conference on High Performance Computer Architecture, 2004, pp. 96-106.
31. D. M. Koppelman, "Neighborhood prefetching on multiprocessors using instruction history," in Proceedings of International Conference on Parallel Architectures and Compilation Techniques, 2000, pp. 123-133.