Future Execution: A Prefetching Mechanism that Uses Multiple Cores to Speed up Single Threads

ACM Transactions on Architecture and Code Optimization

Volumn 3, Issue 4, 2006, Pages 424-449

  Ganusov, Ilya ^a   Burtscher, Martin ^a  

^a Computer Systems Laboratory ^*  (United States)

Author keywords

Chip multiprocessors; Design; Future execution; Memory wall; Performance; Prefetching

Indexed keywords

EID: 47349095223     PISSN: 15443566     EISSN: 15443973     Source Type: Journal    
DOI: 10.1145/1187976.1187979     Document Type: Article

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