Runahead Execution: An Effective Alternative to Large Instruction Windows

IEEE Micro

Volumn 23, Issue 6, 2003, Pages 20-25

  Mutlu, Onur ^a   Stark, Jared ^b   Wilkerson, Chris ^b   Patt, Yale N ^c  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^b INTEL CORPORATION   (United States)

^c The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INSTRUCTION PREFETCHING TECHNIQUES; POWER CONSUMPTION;

ALGORITHMS; BENCHMARKING; CACHE MEMORY; COMPUTATIONAL COMPLEXITY; COMPUTER HARDWARE; CORRELATION METHODS; COST EFFECTIVENESS; DATA REDUCTION; PARALLEL PROCESSING SYSTEMS; RANDOM ACCESS STORAGE; SYSTEMS ANALYSIS;

PROGRAM PROCESSORS;

EID: 1342282617     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2003.1261383     Document Type: Review

References (8)

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5. O. Mutlu et al., "Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors," Proc. 9th IEEE Int'l Symp. High-Performance Computer Architecture (HPCA 03), IEEE CS Press, 2003, pp. 129-140.
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