Gated-Vdd: A circuit technique to reduce leakage in deep-submicron cache memories

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2000, Pages 90-95

  Powell, Michael ^a   Yang, Se Hyun ^a   Falsafi, Babak ^a   Roy, Kaushik ^a   Vijaykumar, T N ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT-LEVEL METHOD; DEEP-SUBMICRON CACHE MEMORIES;

BUFFER STORAGE; CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; ENERGY DISSIPATION; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; MICROELECTRONICS; RANDOM ACCESS STORAGE;

POWER ELECTRONICS;

EID: 0033672408     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)