RDIP: Return-address-stack directed instruction prefetching

MICRO 2013 - Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture

Volumn , Issue , 2013, Pages 260-271

  Kolli, Aasheesh ^a   Saidi, Ali ^b   Wenisch, Thomas F ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

^b ARM LTD   (United Kingdom)

Author keywords

accuracy; caching; instruction fetch; prefetching; RAS

Indexed keywords

ACCURACY; CACHING; INSTRUCTION FETCH; PREFETCHING; RAS;

COMPUTER ARCHITECTURE;

CACHE MEMORY;

EID: 84892524803     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2540708.2540731     Document Type: Conference Paper

References (39)

1. D. Anderson, F. Sparacio, and R. Tomasulo. The IBM System/360 model 91: Machine philosophy and instruction-handling. IBM Journal of Research and Development, 11(1), 1967.
2. M. Annavaram, J. Patel, and E. Davidson. Call graph prefetching for database applications. ACM Trans. on Computer Systems, 21(4), 2003.
3. B. Atikoglu, Y. Xu, E. Frachtenberg, S. Jiang, and M. Paleczny. Workload analysis of a large-scale key-value store. In Proceedings of ACM SIGMETRICS/Performance, 2012.
4. N. Binkert, B. Beckmann, G. Black, S. K. Reinhardt, A. Saidi, A. Basu, J. Hestness, D. R. Hower, T. Krishna, S. Sardashti, R. Sen, K. Sewell, M. Shoaib, N. Vaish, M. D. Hill, and D. A. Wood. The gem5 simulator. SIGARCH Comput. Archit. News, 39(2):1-7, Aug. 2011.
5. I.-C. K. Chen, C.-C. Lee, and T. N. Mudge. Instruction prefetching using branch prediction information. In Proc. of the International Conference on Computer Design, 1997.
6. Facebook. Memcached Tech Talk with M. Zuckerberg, 2010.
7. M. Ferdman, A. Adileh, O. Kocberber, S. Volos, M. Alisafaee, D. Jevdjic, C. Kaynak, A. Popescu, A. Ailamaki, and B. Falsafi. Clearing the clouds: a study of emerging scale-out workloads on modern hardware. In Proc. of the International Conf. on Architectural Support for Programming Languages and Operating Systems, 2012.
8. M. Ferdman, C. Kaynak, and B. Falsafi. Proactive instruction fetch. In Proc. of the International Symposium on Microarchitecture, 2011.
9. M. Ferdman, T. F. Wenisch, A. Ailamaki, B. Falsafi, and A. Moshovos. Temporal instruction fetch streaming. In Proc. of the International Symposium on Microarchitecture, 2008.
10. A. Gutierrez, R. Dreslinski, T. Wenisch, T. Mudge, A. Saidi, C. Emmons, and N. Paver. Full-system analysis and characterization of interactive smartphone applications. In IEEE International Symp. on Workload Characterization, 2011.
11. N. Hardavellas, M. Ferdman, B. Falsafi, and A. Ailamaki. Reactive NUCA: near-optimal block placement and replication in distributed caches. In Proc. of the International Symp. on Computer Architecture, 2009.
12. S. Harizopoulos and A. Ailamaki. STEPS towards cache-resident transaction processing. In Proc. of the International Conf. on Very Large Databases, 2004.
13. R. Hegde. Technical report, Intel, 2008.
14. N. Jouppi. Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers. In Proc. of the International Symp. on Computer Architecture, 1990.
15. C. Kaynak, B. Grot, and B. Falsafi. Shift: Shared history instruction fetch for lean-core server processors. In Proceedings of 46th International Symposium on Microarchitecture, 2013.
16. A.-C. Lai and B. Falsafi. Selective, accurate, and timely self-invalidation using last-touch prediction. In Proceedings of 27th International Symposium on Computer Architecture, 2000.
17. A.-C. Lai, C. Fide, and B. Falsafi. Dead-block prediction & dead-block correlating prefetchers. In Proceedings of 28th International Symposium on Computer Architecture, 2001.
18. K. Lim, D. Meisner, A. Saidi, P. Ranganathan, and T. Wenisch. Thin servers with smart pipes: Designing soc accelerators for memcached. In Proceedings of 40th International Symposium on Computer Architecture, 2013.
19. P. Lotfi-Kamran, B. Grot, M. Ferdman, S. Volos, O. Kocberber, J. Picorel, A. Adileh, D. Jevdjic, S. Idgunji, E. Ozer, et al. Scale-out processors. In Proc. of the International Symp. on Computer Architecture, 2012.
20. C. Luk and T. Mowry. Cooperative prefetching: Compiler and hardware support for effective instruction prefetching in modern processors. In Proc. of the International Symp. on Microarchitecture, 1998.
21. C. Luk and T. Mowry. Architectural and compiler support for effective instruction prefetching: a cooperative approach. ACM Trans. on Computer Systems, 19(1), 2001.
22. O. Mutlu, J. Stark, C. Wilkerson, and Y. N. Patt. Runahead execution: An effective alternative to large instruction windows for out-of-order processors. In Proc. of the International Symp. on High-Performance Computer Architecture, 2003.
23. R. Nair. Dynamic path-based branch correlation. In Proceedings of 28th International Symposium on Microarchitecture, 1995.
24. J. Pierce and T. Mudge. Wrong-path instruction prefetching. In Proc. of the International Symp. on Microarchitecture, 1996.
25. A. Ramirez, L. A. Barroso, K. Gharachorloo, R. Cohen, J. L. Larriba-pey, P. G. Lowney, and M. Valero. Code layout optimizations for transaction processing workloads. In Proc. of the International Symp. on Computer Architecture, 2001.
26. A. Ramirez, O. J. Santana, J. L. Larriba-pey, and M. Valero. Fetching instruction streams. In Proc. of the International Symposium on Microarchitecture, 2002.
27. G. Reinman, B. Calder, and T. Austin. Fetch directed instruction prefetching. In Proc. International Symp. on Microarchitecture, 1999.
28. G. Reinman, B. Calder, and T. Austin. Optimizations enabled by a decoupled front-end architecture. Computers, IEEE Transactions on, 50(4), 2001.
29. P. Saab. Scaling memcached at Facebook, 2008.
30. O. Santana, A. Ramirez, and M. Valero. Enlarging instruction streams. IEEE Transactions on Computers, 56(10), 2007.
31. A. Smith. Sequential program prefetching in memory hierarchies. Computer, 11(12), 1978.
32. L. Spracklen, Y. Chou, and S. G. Abraham. Effective instruction prefetching in chip multiprocessors for modern commercial applications. In Proc. of the International Symp. on High-Performance Computer Architecture, 2005.
33. V. Srinivasan, E. Davidson, G. Tyson, M. Charney, and T. Puzak. Branch history guided instruction prefetching. In Proc. of the International Symp. on High-Performance Computer Architecture, 2001.
34. K. Sundaramoorthy, Z. Purser, and E. Rotenburg. Slipstream processors: Improving both performance and fault tolerance. In Proc. of the International Conf. on Architectural Support for Programming Languages and Operating Systems, 2000.
35. S. Thoziyoor and N. Muralimanohar. Cacti 5.0, 2007.
36. A. V. Veidenbaum. Instruction cache prefetching using multilevel branch prediction. In Proc. of the International Symposium on High Performance Systems, 1997.
37. C. Zhang and S. McKee. Hardware-only stream prefetching and dynamic access ordering. In Proc. of the 14th international conference on Supercomputing, 2000.
38. J. Zhou and K. A. Ross. Buffering database operations for enhanced instruction cache performance. In Proc. of the ACM SIGMOD International Conf. on Management of Data, 2004.
39. C. B. Zilles and G. S. Sohi. Execution-based prediction using speculative slices. In Proc. of the International Symp. in Computer Architecture, 2001.