Icfp: tolerating all-level cache misses in in-order processors

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2009, Pages 431-442

  Hilton, Andrew ^a   Nagarakatte, Santosh ^a   Roth, Amir ^a  

^a UNIVERSITY OF PENNSYLVANIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; COMPUTER ARCHITECTURE; INTEGRATED CIRCUIT DESIGN; MERGING; PIPELINES;

CONTINUAL FLOW PIPELINES; CYCLE-LEVEL SIMULATION; MERGING PROCESS; PIPELINE DESIGN; REGISTER FILES; RUNAHEAD EXECUTION; SINGLE-THREAD PERFORMANCE; TRACKING SCHEME;

PIPELINE PROCESSING SYSTEMS;

EID: 64949124579     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2009.4798281     Document Type: Conference Paper

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