Techniques for bandwidth-efficient prefetching of Linked Data Structures in hybrid prefetching systems

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2009, Pages 7-17

  Ebrahimi, Eiman ^a   Mutlu, Onur ^b   Patt, Yale N ^a  

^a The University of Texas at Austin   (United States)

^b CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; COMPUTER HARDWARE DESCRIPTION LANGUAGES; DATA HANDLING; DATA STRUCTURES; DIGITAL STORAGE; LINKED DATA;

BANDWIDTH EFFICIENCY; BANDWIDTH EFFICIENT; COOPERATIVE TECHNIQUES; FILTERING MECHANISM; LARGE-SCALE APPLICATIONS; PREFETCHING TECHNIQUES; RESOURCE CONTENTION; THROTTLING MECHANISM;

COMPUTER ARCHITECTURE;

EID: 64949179220     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2009.4798232     Document Type: Conference Paper

References (43)

1. A.-R. Adl-Tabatabai et al. Prefetch injection based on hardware monitoring and object metadata. In PLDI, 2004.
2. H. Al-Sukhni, I. Bratt, and D. A. Connors. Compiler directed contentaware prefetching for dynamic data structures. In PACT-12, 2003.
3. C. Alkan et al. Structural variation detection using high-throughput sequencing. In Pacific Symposium on Biocomputing, 2008.
4. M. Annavaram et al. Data prefetching by dependence graph precomputation. In ISCA-29, 2001.
5. M. J. Charney and A. P. Reeves. Generalized correlation-based hardware prefetching. Technical Report EE-CEG-95-1, Cornell Univ., 1995.
6. J. D. Collins et al. Speculative precomputation: long-range prefetching of delinquent loads. In ISCA-28, 2001.
7. J. D. Collins, S. Sair, B. Calder, and D.M. Tullsen. Pointer cache assisted prefetching. In MICRO-35, 2002.
8. J. D. Collins, D. M. Tullsen, H. Wang, and J. P. Shen. Dynamic speculative precomputation. In MICRO-34, 2001.
9. R. Cooksey, S. Jourdan, and D. Grunwald. A stateless, content-directed data prefetching mechanism. In ASPLOS-X, 2002.
10. J. Doweck. Inside Intel Core Microarchitecture and Smart Memory Access - White Paper. Intel, Jul 2006.
11. A. Gendler et al. A pab-based multi-prefetcher mechanism. International Journal of Parallel Programming, 34(2):171-478, Apr. 2006.
12. J. D. Gindele. Buffer block prefetching method. IBM Technical Disclosure Bulletin, 20(2):696-697, July 1977.
13. G. Hinton et al. The microarchitecture of the Pentium 4 processor. Intel Technology Journal, Feb. 2001. Q1 2001 Issue.
14. M. Horowitz et al. Informingmemory operations: providing memory performance feedback in modern processors. In ISCA-23, 1996.
15. Z. Hu, M. Martonosi, and S. Kaxiras. TCP: Tag Correlating Prefetchers. In HPCA-8, 2002.
16. K. J.Nesbit and J. E.Smith. Data cache prefetching using a global history buffer. In HPCA-10, 2004.
17. D. Joseph and D. Grunwald. Prefetching using Markov predictors. In ISCA-24, 1997.
18. N. Jouppi. Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers. In ISCA-17, 1990.
19. A. KleinOsowski and D. Lilja. MinneSPEC: A new SPEC benchmark workload for simulation-based computer architecture research. Comp Arch Letters, 2002.
20. A.-C. Lai, C. Fide, and B. Falsafi. Dead-block prediction and dead-block correlating prefetchers. In ISCA-28, 2001.
21. H. Lieberman and C. Hewitt. A real-time garbage collector based on the lifetimes of objects. ACM Communications, 26, June 1983.
22. M. H. Lipasti et al. SPAID: Software prefetching in pointer- and callintensive environments. In MICRO-28, 1995.
23. C.-K. Luk. Tolerating memory latency through software-controlled preexecution in simultaneous multithreading processors. In ISCA, 2001.
24. C.-K. Luk and T. C. Mowry. Compiler-based prefetching for recursive data structures. In ASPLOS-7, 1996.
25. K. Luo, J. Gummaraju, and M. Franklin. Balancing throughput and fairness in SMT processors. In ISPASS, 2001.
26. O. Mutlu et al. Address-value delta (AVD) prediction: Increasing the effectiveness of runahead execution by exploting regular memory allocation patterns. In MICRO-38, 2005.
27. S. Palacharla and R. E. Kessler. Evaluating stream buffers as a secondary cache replacement. In ISCA-21, 1994.
28. D. G. Perez et al. Microlib: A case for the quantitative comparison of micro-architecture mechanisms. In MICRO-37, 2004.
29. A. Rogers et al. Supporting dynamic data structures on distributed memory machines. ACM TOPLAS, 17(2), Mar. 1995.
30. A. Roth, A. Moshovos, and G. S. Sohi. Dependence based prefetching for linked data structures. In ASPLOS-8, 1998.
31. A. Roth and G. S. Sohi. Effective jump-pointer prefetching for linked data structures. In ISCA-26, 1999.
32. T. Sherwood, E. Perelman, G. Hamerly, and B. Calder. Automatically characterizing large scale program behavior. In ASPLOS-X, 2002.
33. A. Snavely and D. M. Tullsen. Symbiotic job scheduling for a simultaneous multithreading processor. In ASPLOS-IX, 2000.
34. Y. Solihin, J. Lee, and J. Torrellas. Using a user-level memory thread for correlation prefetching. In ISCA-29, 2002.
35. S. Somogyi et al. Spatial memory streaming. In ISCA-33, 2006.
36. S. Srinath et al. Feedback directed prefetching: Improving the performance and bandwidth-efficiency of hardware prefetchers. In HPCA, 2007.
37. V. Srinivasan et al. A static filter for reducing prefetch traffic. Technical Report CSE-TR-400-99, University of Michigan, 1999.
38. J. Tendler, S. Dodson, S. Fields, H. Le, and B. Sinharoy. POWER4 system microarchitecture. IBM Technical White Paper, Oct. 2001.
39. Z. Wang et al. Guided region prefetching: a cooperative hardware/software approach. In ISCA-30, 2003.
40. C.-L. Yang and A. R. Lebeck. Push vs. pull: Data movement for linked data structures. In ICS-2000, 2000.
41. X. Zhuang and H.-H. S. Lee. A hardware-based cache pollution filtering mechanism for aggressive prefetches. In ICPP-32, 2003.
42. C. Zilles. Benchmark health considered harmful. Computer Architecture News, 29(3), 2001.
43. C. Zilles and G. Sohi. Execution-based prediction using speculative slices. In ISCA-28, 2001.