Continual flow pipelines

11th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS XI

Volumn , Issue , 2004, Pages 107-119

  Srinivasan, Srikanth T ^a   Rajwar, Ravi ^a   Akkary, Haitham ^a   Gandhi, Amit ^a   Upton, Mike ^a  

^a INTEL CORPORATION   (United States)

Author keywords

CFP; Instruction Window; Latency Tolerance; Non blocking

Indexed keywords

BUFFER STORAGE; COMPUTER ARCHITECTURE; COMPUTER SYSTEM RECOVERY; FAULT TOLERANT COMPUTER SYSTEMS; MICROPROCESSOR CHIPS; PIPELINES; SCHEDULING; THROUGHPUT;

CFP; CONTINUAL FLOW PIPELINES; INSTRUCTION WINDOW; LATENCY TOLERANCE; NON-BLOCKING;

COMPUTER NETWORKS;

EID: 12844269176     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1024393.1024407     Document Type: Conference Paper

References (23)

1. H. Akkary and M. A. Driscoll. A Dynamic Multithreading Processor. In Proceedings of the 31st International Symposium on Microarchitecture, November 1998.
2. H. Akkary, R. Rajwar, and S. T. Srinivasan. Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors. In Proceedings of the 36th International Symposium on Microarchitecture, December 2003.
3. R. Balasubramonian, S. Dwarkadas, and D. Albonesi. Reducing the complexity of the register file in dynamic superscalar processors. In Proceedings of the 34th International Symposium on Microarchitecture, December 2001, pp. 237-249.
4. R. Balasubramonian, S. Dwarkadas, and D. H. Albonesi. Dynamically allocating processor resources between nearby and distant ILP. In Proceedings of the 28th Annual International Symposium on Computer Architecture, June 2001, pp. 26-37.
5. D. Burger, S. Kaxiras, and J. R. Goodman. DataScalar Architectures. In Proceedings of the 24th Annual International Symposium on Computer Architecture, June 1997, pp. 338-349.
6. R. Chappell, J. Stark, S. Kim, S. Reinhardt, and Y. Patt. Simultaneous Subordinate Multithreading (SSMT). In Proceedings of the 26th Annual International Symposium on Computer Architecture, May 1999.
7. G. Z. Chrysos and J. S. Emer. Memory dependence prediction using store sets. In Proceedings of the 25th Annual International Symposium on Computer Architecture, June 1998, pp. 142-153.
8. A. Cristal, D. Ortega, J. Llosa, and M. Valero. Out-of-Order Commit Processors. In Proceedings of the Tenth International Symposium on High-Performance Computer Architecture, February 2004, pp. 48-59.
9. A. Cristal, M. Valero, J.-L. Llosa, and A. Gonzalez. Large Virtual ROBs by Processor Checkpointing. Technical Report UPC-DAC-2002-39, Universitat Politecnica de Catalunya, July 2002.
10. J.-L. Cruz, A. Gonzalez, M. Valero, and N. P. Topham. Multiple-banked register file architectures. In Proceedings of the 28th Annual International Symposium on Computer Architecture, June 200.
11. J. Dundas and T. Mudge. Improving data cache performance by pre-executing instructions under a cache miss. In Proceedings of the 1997 International Conference on Supercomputing, 1997, pp. 68-75.
12. G. Hinton, D. Sager, M. Upton, D. Boggs, D. Carmean, A. Kyker, and P. Roussel. The Microarchitecture of the Pentium 4 Processor. Intel Technology Journal, February 2001.
13. T. Karkhanis and J. E. Smith. A Day in the Life of a Data Cache Miss. In Workshop on Memory Performance Issues, June 2002.
14. A. R. Lebeck, J. Koppanalil, T. Li, J. Patwardhan, and E. Rotenberg. A large, fast instruction window for tolerating cache misses. In Proceedings of the 29th Annual International Symposium on Computer Architecture, May 2002, pp. 59-70.
15. J. F. Martinez, J. Renau, M. C. Huang, M. Prvulovic, and J. Torrellas. Cherry: Checkpointed Early Resource Recycling in Out-of-order Microprocessors. In Proceedings of the 35th International Symposium on Microarchitecture, November 2002.
16. T. Monreal, A. González, M. Valero, J. González, and V. Viñals. Dynamic Register Renaming Through Virtual-Physical Registers. In Journal of Instruction Level Parallelism, May 2000.
17. M. Moudgill, K. Pingali, and S. Vassiliadis. Register Renaming and Dynamic Speculation: an alternative Approach. In Proceedings of the 26th International Symposium on Microarchitecture, December 1993.
18. O. Mutlu, J. Stark, C. Wilkerson, and Y. N. Patt. Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors. In Proceedings of the Ninth International Symposium on High-Performance Computer Architecture, February 2003.
19. A. Roth and G. S. Sohi. Speculative Data-Driven Multi-Threading. In Proceedings of the Seventh International Symposium on High-Performance Computer Architecture, January 2001.
20. K. Sankaralingam, R. Nagarajan, H. Liu, C. Kim, J. Huh, D. Burger, S. W. Keckler, and C. R. Moore. Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture. In Proceedings of the 30th Annual International Symposium on Computer Architecture, June 2003.
21. G. S. Sohi, S. E. Breach, and T. N. Vijaykumar. Multiscalar Processors. In Proceedings of the 22nd Annual International Symposium on Computer Architecture, June 1995, pp. 414-425.
22. Y. Song and M. Dubois, Assisted Execution. University of Southern California, Technical Report #CENG 98-25, Department of EE-Systems. October 1998.
23. C. B. Zilles and G. S. Sohi. Execution-based prediction using speculative slices. In Proceedings of the 28th Annual International Symposium on Computer Architecture, June 2001, pp. 2-13.