-
2
-
-
2842517957
-
The IBM system/360 model 91: Machine philosophy and instruction handling
-
D. W. Anderson, F. J. Sparacio, and R. M. Tomasulo. The IBM system/360 model 91: Machine philosophy and instruction handling. IBM Journal of Research and Development, 11(1):8-24, 1967.
-
(1967)
IBM Journal of Research and Development
, vol.11
, Issue.1
, pp. 8-24
-
-
Anderson, D.W.1
Sparacio, F.J.2
Tomasulo, R.M.3
-
3
-
-
2442585659
-
Call graph prefetching for database applications
-
M. Annavaram, J. M. Patel, and E. S. Davidson. Call graph prefetching for database applications. ACM Transactions on Computer Systems, 21(4):412-444, 2003.
-
(2003)
ACM Transactions on Computer Systems
, vol.21
, Issue.4
, pp. 412-444
-
-
Annavaram, M.1
Patel, J.M.2
Davidson, E.S.3
-
7
-
-
47349132413
-
Low-cost epoch-based correlation prefetching for commercial applications
-
Dec
-
Y. Chou. Low-cost epoch-based correlation prefetching for commercial applications. 40th Annual Int'l Symposium on Microarchitecture, Dec. 2007.
-
(2007)
40th Annual Int'l Symposium on Microarchitecture
-
-
Chou, Y.1
-
9
-
-
0019596071
-
Trace scheduling: A technique for global microcode compaction
-
Jul
-
J. A. Fisher. Trace scheduling: A technique for global microcode compaction. IEEE Transactions on Computers, C-30(7):478-490, Jul. 1981.
-
(1981)
IEEE Transactions on Computers
, vol.C-30
, Issue.7
, pp. 478-490
-
-
Fisher, J.A.1
-
11
-
-
84863354514
-
Database servers on Chip Multiprocessors: Limitations and Opportunities
-
N. Hardavellas, I. Pandis, R. Johnson, N. Mancheril, A. Ailamaki, and B. Falsafi. Database servers on Chip Multiprocessors: Limitations and Opportunities. 3rd Biennial Conference on Innovative Data Systems Research, 2007.
-
(2007)
3rd Biennial Conference on Innovative Data Systems Research
-
-
Hardavellas, N.1
Pandis, I.2
Johnson, R.3
Mancheril, N.4
Ailamaki, A.5
Falsafi, B.6
-
14
-
-
0025429331
-
Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
-
May
-
N. P. Jouppi. Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers. Proc. 17th Annual Int'l Symposium on Computer Architecture, May 1990.
-
(1990)
Proc. 17th Annual Int'l Symposium on Computer Architecture
-
-
Jouppi, N.P.1
-
15
-
-
0031594019
-
Performance characterization of a quad Pentium Pro SMP using OLTP workloads
-
Jun
-
K. Keeton, D. A. Patterson, Y. Q. He, R. C. Raphael, and W. E. Baker. Performance characterization of a quad Pentium Pro SMP using OLTP workloads. Proc. 25th Annual Int'l Symposium on Computer Architecture, Jun. 1998.
-
(1998)
Proc. 25th Annual Int'l Symposium on Computer Architecture
-
-
Keeton, K.1
Patterson, D.A.2
He, Y.Q.3
Raphael, R.C.4
Baker, W.E.5
-
17
-
-
0031594020
-
An analysis of database workload performance on simultaneous multithreaded processors
-
Jun
-
J. L. Lo, L. A. Barroso, S. J. Eggers, K. Gharachorloo, H. M. Levy, and S. S. Parekh. An analysis of database workload performance on simultaneous multithreaded processors. Proc. 25th Annual Int'l Symposium on Computer Architecture, Jun. 1998.
-
(1998)
Proc. 25th Annual Int'l Symposium on Computer Architecture
-
-
Lo, J.L.1
Barroso, L.A.2
Eggers, S.J.3
Gharachorloo, K.4
Levy, H.M.5
Parekh, S.S.6
-
18
-
-
0034839064
-
Tolerating memory latency through software-controlled pre-execution in simultaneous multithreading processors
-
Jun
-
C.-K. Luk. Tolerating memory latency through software-controlled pre-execution in simultaneous multithreading processors. Proc. 28th Annual Int'l Symposium on Computer Architecture, Jun. 2001.
-
(2001)
Proc. 28th Annual Int'l Symposium on Computer Architecture
-
-
Luk, C.-K.1
-
19
-
-
0032308865
-
Cooperative prefetching: Compiler and hardware support for effective instruction prefetching in modern processors
-
Dec
-
C.-K. Luk and T. C. Mowry. Cooperative prefetching: compiler and hardware support for effective instruction prefetching in modern processors. Proc. 31st Annual Int'l Symposium on Microarchitecture, Dec. 1998.
-
(1998)
Proc. 31st Annual Int'l Symposium on Microarchitecture
-
-
Luk, C.-K.1
Mowry, T.C.2
-
20
-
-
1342282617
-
Runahead execution: An effective alternative to large instruction windows
-
Nov./Dec
-
O. Mutlu, J. Stark, C. Wilkerson, and Y. N. Patt. Runahead execution: an effective alternative to large instruction windows. IEEE Micro, 23(6):20-25, Nov./Dec. 2003.
-
(2003)
IEEE Micro
, vol.23
, Issue.6
, pp. 20-25
-
-
Mutlu, O.1
Stark, J.2
Wilkerson, C.3
Patt, Y.N.4
-
22
-
-
0034838875
-
Code layout optimizations for transaction processing workloads
-
Jun
-
A. Ramirez, L. A. Barroso, K. Gharachorloo, R. Cohn, J. Larriba-Pey, P.G. Lowney, and M. Valero. Code layout optimizations for transaction processing workloads. Proc. 28th Annual Int'l Symposium on Computer Architecture, Jun. 2001.
-
(2001)
Proc. 28th Annual Int'l Symposium on Computer Architecture
-
-
Ramirez, A.1
Barroso, L.A.2
Gharachorloo, K.3
Cohn, R.4
Larriba-Pey, J.5
Lowney, P.G.6
Valero, M.7
-
25
-
-
0035308287
-
Optimizations enabled by a decoupled front-end architecture
-
G. Reinman, B. Calder, and T. M. Austin. Optimizations enabled by a decoupled front-end architecture. IEEE Transactions Computers, 50(4):338-355, 2001.
-
(2001)
IEEE Transactions Computers
, vol.50
, Issue.4
, pp. 338-355
-
-
Reinman, G.1
Calder, B.2
Austin, T.M.3
-
27
-
-
34548767664
-
Enlarging instruction streams
-
O. J. Santana, A. Ramirez, and M. Valero. Enlarging instruction streams. IEEE Transactions Computers, 56(10): 1342-1357, 2007.
-
(2007)
IEEE Transactions Computers
, vol.56
, Issue.10
, pp. 1342-1357
-
-
Santana, O.J.1
Ramirez, A.2
Valero, M.3
-
29
-
-
0018106484
-
Sequential program prefetching in memory hierarchies
-
A. J. Smith. Sequential program prefetching in memory hierarchies. Computer, 11(12):7-21, 1978.
-
(1978)
Computer
, vol.11
, Issue.12
, pp. 7-21
-
-
Smith, A.J.1
-
32
-
-
0034818890
-
Branch history guided instruction prefetching
-
V. Srinivasan, E. S. Davidson, G. S. Tyson, M. J. Charney, and Thomas R. Puzak. Branch history guided instruction prefetching. 7th Int'l Symposium on High-Performance Computer Architecture, 2001.
-
(2001)
7th Int'l Symposium on High-Performance Computer Architecture
-
-
Srinivasan, V.1
Davidson, E.S.2
Tyson, G.S.3
Charney, M.J.4
Puzak, T.R.5
-
35
-
-
66749129714
-
-
PhD Thesis, Carnegie Mellon University, Aug
-
T. F. Wenisch. Temporal Memory Streaming. PhD Thesis, Carnegie Mellon University, Aug. 2007.
-
(2007)
Temporal Memory Streaming
-
-
Wenisch, T.F.1
-
36
-
-
56449097232
-
Temporal streams in commercial server applications
-
Sept
-
T. F. Wenisch, M. Ferdman, A. Ailamaki, B. Falsafi, and A. Moshovos. Temporal streams in commercial server applications. Proc. IEEE Int'l Symposium on Workload Characterization, Sept. 2008.
-
(2008)
Proc. IEEE Int'l Symposium on Workload Characterization
-
-
Wenisch, T.F.1
Ferdman, M.2
Ailamaki, A.3
Falsafi, B.4
Moshovos, A.5
-
37
-
-
27544508955
-
Temporal streaming ofshared memory
-
Jun
-
T. F. Wenisch, S. Somogyi, N. Hardavellas, J. Kim, A. Ailamaki, and B. Falsafi. Temporal streaming ofshared memory. Proc. 32nd Annual Int'l Symposium on Computer Architecture, Jun. 2005.
-
(2005)
Proc. 32nd Annual Int'l Symposium on Computer Architecture
-
-
Wenisch, T.F.1
Somogyi, S.2
Hardavellas, N.3
Kim, J.4
Ailamaki, A.5
Falsafi, B.6
-
38
-
-
33748289310
-
SimFlex: Statistical sampling of computer system simulation
-
Jul.-Aug
-
T. F. Wenisch, R. E. Wunderlich, M. Ferdman, A. Ailamaki, B. Falsafi, and J. C. Hoe. SimFlex: statistical sampling of computer system simulation. IEEE Micro, 26(4): 18-31, Jul.-Aug. 2006.
-
(2006)
IEEE Micro
, vol.26
, Issue.4
, pp. 18-31
-
-
Wenisch, T.F.1
Wunderlich, R.E.2
Ferdman, M.3
Ailamaki, A.4
Falsafi, B.5
Hoe, J.C.6
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