Dark silicon and the end of multicore scaling

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2011, Pages 365-376

  Esmaeilzadehy, Hadi ^a   Blemz, Emily ^b   St Amantx, Renée ^c   Sankaralingamz, Karthikeyan ^b   Burgerfi, Doug ^d  

^a UNIVERSITY OF WASHINGTON   (United States)

^b UNIVERSITY OF WISCONSIN MADISON   (United States)

^c UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^d MICROSOFT RESEARCH   (United States)

Author keywords

Dark silicon; Modeling; Multicore; Power; Technology scaling

Indexed keywords

COMPUTING COMMUNITY; DARK SILICON; DEVICE-SCALING; MOORE'S LAW; MULTI CORE; MULTICORE CHIPS; MULTICORE DESIGN; PAPER MODELS; PARETO-OPTIMAL FRONTIERS; PERFORMANCE MODEL; POWER; PROCESSOR DESIGNERS; SCALING LIMITS; SINGLE-THREADED; TECHNOLOGY SCALING;

PARALLEL PROCESSING SYSTEMS; TOPOLOGY; COMPUTER ARCHITECTURE; MODELS;

COMPUTER ARCHITECTURE; PARALLEL PROCESSING SYSTEMS;

EID: 80052528714     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2000064.2000108     Document Type: Conference Paper

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