Stream chaining: Exploiting multiple levels of correlation in data prefetching

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2009, Pages 81-92

  Díaz, Pedro ^a   Cintra, Marcelo ^a  

^a UNIVERSITY OF EDINBURGH   (United Kingdom)

Author keywords

Data prefetchin

Indexed keywords

DATA-PREFETCHING; MEMORY ACCESS; MEMORY BANDWIDTHS; MEMORY WALL; MULTI-CORE SYSTEMS; MULTIPLE LEVELS; MULTIPLE STREAMS; PREFETCHES; PREFETCHING; TIME SEQUENCES;

COMPUTERS; HYDRAULICS; MICROPROCESSOR CHIPS;

COMPUTER ARCHITECTURE;

EID: 70450233836     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1555754.1555767     Document Type: Conference Paper

References (23)

1. K. Albayraktaroglu, A. Jaleel, X. Wu, M. Franklin, B. Jacob, C.-W. Tseng, and D. Yeung. "BioBench: A benchmark suite of bioinformatics applications." Intl. Symp. on Performance Analysis of Systems and Software, pages 2-9, March 2005.
2. J.-L. Baer and T. F. Chen. "An Effective On-Chip Preloading Scheme to Reduce Data Access Penalty." Supercomputing Conf., pages 176-186, November 1991.
3. J. Doweck. "Inside Intel Core Microarchitecture and Smart Memory Access." White paper, Intel Corporation, 2006. http://download.intel.com/ technology/architecture/sma.pdf.
4. J. W. C. Fu, J. H. Patel, and B. L. Janssens. "Stride Directed Prefetching in Scalar Processors." Intl. Symp. on Microarchitecture, pages 102-110, December 1992.
5. Z. Hu, S. Kaxiras, and M. Martonosi. "Timekeeping in the Memory System: Predicting and Optimizing Memory Behavior." Intl. Symp. on Computer Architecture, pages 209-220, May 2002.
6. Z. Hu, M. Martonosi, and S. Kaxiras. "TCP: Tag Correlating Prefetchers." Intl. Symp. on High Performance Computer Architecture, pages 317-326, February 2003.
7. N. Jouppi. "Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers." Intl. Symp. on Computer Architecture, pages 364-373, May 1990.
8. D. Joseph and D. Grunwald. "Prefetching Using Markov Predictors." Intl. Symp. on Computer Architecture, pages 252-263, June 1997.
9. G. B. Kandiraju and A. Sivasubramaniam. "Going the Distance for TLB Prefetching: An Application-Driven Study." Intl. Symp. on Computer Architecture, pages 195-206, May 2002.
10. A.-C. Lai, C. Fide, and B. Falsafi. "Dead-Block Prediction & Dead-Block Correlating Prefetchers." Intl. Symp. on Computer Architecture, pages 144-154, June 2001.
11. H. Q. Le, W. J. Starke, J. Stephen Fields, F. P. O'Connell, D. Q. Nguyen, B. J. Ronchetti, W. M. Sauer, E. M. Schwarz, and M. T. Vaden. "IBM POWER6 Microarchitecture." IBM Journal of Research and Development, vol. 51, no. 6, pages 639-662, November 2007.
12. K. J. Nesbit and J. E. Smith. "Data Cache Prefetching Using a Global History Buffer." Intl. Symp. on High Performance Computer Architecture, pages 96-106, February 2004.
13. K. J. Nesbit, A. S. Dhodapkar, and J. E. Smith. "AC/DC: An Adaptive Data Cache Prefetcher." Intl. Conf. on Parallel Architectures and Compilation Techniques, pages 135-145, September 2004.
14. S. Palacharla and R. E. Kessler. "Evaluating Stream Buffers as a Secondary Cache Replacement." Intl. Symp. on Computer Architecture, pages 24-33, May 1994.
15. D. G. Pärez, G. Mouchard, and O. Temam. "MicroLib: A Case for the Quantitative Comparison of Micro-Architecture Mechanisms." Intl. Symp. on Microarchitecture, pages 43-54, December 2004.
16. J. Renau, B. Fraguela, J. Tuck, W. Liu, M. Prvulovic, L. Ceze, S. Sarangi, P. Sack, K. Strauss, and P. Montesinos. SESC simulator. http://sesc.sf.net
17. P. Shivakumar and N. P. Jouppi. CACTI 3.0: An Integrated Cache Timing, Power, and Area Model. WRL Research Report, 2001/2.
18. Y. Solihin, J. Lee, and J. Torrellas. "Using a User-Level Memory Thread for Correlation Prefetching." Intl. Symp. on Computer Architecture, pages 171-182, May 2002.
19. S. Somogyi, T. F. Wenisch, A. Ailamaki, B. Falsafi, and A. Moshovos. "Spatial Memory Streaming." Intl. Symp. on Computer Architecture, pages 252-263, June 2006.
20. S. Somogyi, T. F. Wenisch, A. Ailamaki, and B. Falsafi. "Spatio-Temporal Memory Streaming." Intl. Symp. on Computer Architecture, June 2009.
21. V. Srinivasan, E. S. Davidson, G. S. Tyson, M. J. Charney, and T. R. Puzak. "Branch History Guided Instruction Prefetching." Intl. Symp. on High Performance Computer Architecture, pages 291-300, January 2001.
22. T. F. Wenisch, S. Somogyi, N. Hardavellas, J. Kim, A. Aila-maki, and B. Falsafi. "Temporal Streaming of Shared Memory." Intl. Symp. on Computer Architecture, pages 222-233, June 2005.
23. W. Zhang, B. Calder, and D. M. Tullsen. "A Self-Repairing Prefetcher in an Event-Driven Optimization Framework." Intl. Symp. on Code Generation and Optimization, pages 50-64, March 2006.