Runahead execution: An alternative to very large instruction windows for out-of-order processors

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn 12, Issue , 2003, Pages 129-140

  Mutlu, O ^a   Stark, J ^b   Wilkerson, C ^b   Patt, Y N ^a  

^a UNIVERSITY OF TEXAS   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Delay; Energy consumption; Engines; Hardware; Microprocessors; Out of order; Prefetching; Software; Trademarks; Windows

Indexed keywords

BUFFER STORAGE; COMPUTER HARDWARE; COMPUTER SOFTWARE; ENERGY UTILIZATION; ENGINES; MEMORY ARCHITECTURE; MICROPROCESSOR CHIPS; PROGRAM PROCESSORS; SUPERCOMPUTERS; TRADEMARKS; WINDOWS;

DELAY; HIGH PERFORMANCE PROCESSORS; INSTRUCTIONS PER CYCLES; LARGE INSTRUCTION WINDOW; OUT OF ORDER; OUT-OF-ORDER EXECUTION; OUT-OF-ORDER PROCESSORS; PREFETCHING;

COMPUTER ARCHITECTURE;

EID: 84955506994     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2003.1183532     Document Type: Conference Paper

References (31)

1. J. L. Aragón, J. González, A. González, J. E. Smith. Dual path instruction processing. In Proceedings of the 2002 International Conference on Supercomputing, 2002.
2. J. Baer and T. Chen. An effective on-chip preloading scheme to reduce data access penalty. In Proceedings of Supercomputing '91, 1991.
3. R. Balasubramonian, S. Dwarkadas, D. H. Albonesi. Dynamically allocating processor resources between nearby and distant ILP. In Proceedings of the 28th Annual International Symposium on Computer Architecture, 2001.
4. BAPCo?. BAPCo Benchmarks. http://www.bapco.com/.
5. D. Callahan, K. Kennedy, A. Porterfield. Software prefetching. In Proceedings of the 4th International Conference on Architectural Support for Programming Languages and Operating Systems, 1991.
6. R. S. Chappell, J. Stark, S. P. Kim, S. K. Reinhardt, Y. N. Patt. Simultaneous subordinate microthreading (SSMT). In Proceedings of the 26th Annual International Symposium on Computer Architecture, 1999.
7. G. Z. Chrysos and J. S. Emer. Memory dependence prediction using store sets. In Proceedings of the 25th Annual International Symposium on Computer Architecture, 1998.
8. J. D. Collins, D. M. Tullsen, H. Wang, J. P. Shen. Dynamic speculative precomputation. In Proceedings of the 34th Annual ACM/IEEE International Symposium on Microarchitecture, 2001.
9. R. Cooksey. Content-Sensitive Data Prefetching. PhDthesis, University ofC olorado, Boulder, 2002.
10. J. Dundas and T. Mudge. Improving data cache performance by pre-executing instructions under a cache miss. In Proceedings of the 1997 International Conference on Supercomputing, 1997.
11. J. D. Dundas. Improving Processor Performance by Dynamically Pre-Processing the Instruction Stream. PhD thesis, University ofMi chigan, 1998.
12. L. Gwennap. Intel's P6 uses decoupled superscalar design. Microprocessor Report, Feb. 1995.
13. G. Hinton, D. Sager, M. Upton, D. Boggs, D. Carmean, A. Kyker, P. Roussel. The microarchitecture oft he Pentium 4 processor. Intel Technical Journal, Feb. 2001. Q1 2001 Issue.
14. Intel Corporation. Intel Pentium 4 Processor Optimization Reference Manual, 1999.
15. D. A. Jiménez and C. Lin. Dynamic branch prediction with perceptrons. In Proceedings of the Seventh IEEE International Symposium on High Performance Computer Architecture, 2001.
16. D. Joseph and D. Grunwald. Prefetching using Markov predictors. In Proceedings of the 24th Annual International Symposium on Computer Architecture, 1997.
17. N. P. Jouppi. Improving direct-mapped cache performance by the addition ofa small fully-associative cache and prefetch buffers. In Proceedings of the 17th Annual International Symposium on Computer Architecture, 1990.
18. R. E. Kessler. The Alpha 21264 microprocessor. IEEE Micro, 19(2), 1999.
19. D. Kroft. Lockup-free instruction fetch/prefetch cache organization. In Proceedings of the 8th Annual International Symposium on Computer Architecture, 1981.
20. A. R. Lebeck, J. Koppanalil, T. Li, J. Patwardhan, E. Rotenberg. A large, fast instruction window for tolerating cache misses. In Proceedings of the 29th Annual International Symposium on Computer Architecture, 2002.
21. C.-K. Luk. Tolerating memory latency through softwarecontrolled pre-execution in simultaneous multithreading processors. In Proceedings of the 28th Annual International Symposium on Computer Architecture, 2001.
22. C.-K. Luk and T. C. Mowry. Compiler-based prefetching for recursive data structures. In Proceedings of the 7th International Conference on Architectural Support for Programming Languages and Operating Systems, 1996.
23. A. Moshovos and G. S. Sohi. Streamlining inter-operation memory communication via data dependence prediction. In Proceedings of the 30th Annual ACM/IEEE International Symposium on Microarchitecture, 1997.
24. T. C. Mowry, M. S. Lam, A. Gupta. Design and evaluation of a compiler algorithm for prefetching. In Proceedings of the 5th International Conference on Architectural Support for Programming Languages and Operating Systems, 1992.
25. E. Sprangle and D. Carmean. Increasing processor performance by implementing deeper pipelines. In Proceedings of the 29th Annual International Symposium on Computer Architecture, 2002.
26. The Standard Performance Evaluation Corporation. Welcome to SPEC. http://www.spec.org/.
27. TimesTen, Inc. TimesTen. http://www.timesten.com/.
28. VeriTest?. Ziff Davis Media benchmarks. http://www.etestinglabs.com/benchmarks/.
29. M. V. Wilkes. Slave memories and dynamic storage allocation. IEEE Transactions on Electronic Computers, 14(2), 1965.
30. K. C. Yeager. The MIPS R10000 superscalar microprocessor. IEEE Micro, 16(2), Apr. 1996.
31. C. Zilles and G. Sohi. Execution-based prediction using speculative slices. In Proceedings of the 28th Annual International Symposium on Computer Architecture, 2001.