Fetching instruction streams

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn 2002-January, Issue , 2002, Pages 371-382

  Ramirez, Alex ^a   Santana, Oliverio J ^a   Larriba Pey, Josep L ^a   Valero, Mateo ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

Computer architecture; Cost function; Engines; Hip; Process design

Indexed keywords

CODES (SYMBOLS); COST FUNCTIONS; ENGINES; HOT ISOSTATIC PRESSING; INTEGRATED CIRCUIT LAYOUT; PROCESS DESIGN;

ARCHITECTURE-BASED; BRANCH PREDICTORS; INSTRUCTION STREAMS; PERFORMANCE LEVEL; PROCESSOR DESIGN; PROCESSOR PERFORMANCE; STATE OF THE ART; SUPERSCALAR PROCESSOR;

COMPUTER ARCHITECTURE;

EID: 84948990915     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2002.1176264     Document Type: Conference Paper

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