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Volumn , Issue , 2007, Pages 301-313

Low-cost epoch-based correlation prefetching for commercial applications

Author keywords

[No Author keywords available]

Indexed keywords

ACCESS CONTROL; BENCHMARKING; DATA PROCESSING; DATA STORAGE EQUIPMENT;

EID: 47349132413     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2007.39     Document Type: Conference Paper
Times cited : (52)

References (41)
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    • Smith, A.1
  • 7
    • 0010351452 scopus 로고    scopus 로고
    • A Performance Study of Instruction Cache Prefetching Methods
    • May
    • W. Hsu and J. Smith, "A Performance Study of Instruction Cache Prefetching Methods," in IEEE Transactions on Computers, vol. 47, pp. 497-508, May 1998.
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    • Hsu, W.1    Smith, J.2
  • 11
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    • Improving Direct-Mapped Cache Performance by the Addition of a Small Fully Associative Cache and Prefetch Buffers
    • N. Jouppi, "Improving Direct-Mapped Cache Performance by the Addition of a Small Fully Associative Cache and Prefetch Buffers," in Proceedings of 17th Annual International Symposium on Computer Architecture, 1990.
    • (1990) Proceedings of 17th Annual International Symposium on Computer Architecture
    • Jouppi, N.1
  • 14
    • 0029308368 scopus 로고
    • Effective Hardware-Based Data Prefetching for High Performance Processors
    • T. Chen et al, "Effective Hardware-Based Data Prefetching for High Performance Processors," in IEEE Transactions on Computers, pp. 609-623, 1995.
    • (1995) IEEE Transactions on Computers , pp. 609-623
    • Chen, T.1
  • 17
    • 0016930686 scopus 로고
    • Dynamic Improvements of Locality in Virtual Memory Systems
    • March
    • J. Baer, "Dynamic Improvements of Locality in Virtual Memory Systems," in IEEE Transactions on Software Engineering, March 1976.
    • (1976) IEEE Transactions on Software Engineering
    • Baer, J.1
  • 18
    • 0009596875 scopus 로고
    • Prefetching System for a Cache Having a Second Directory for Sequentially Accessed Blocks,
    • U.S. Patent 4,807,110, February
    • J. Pomerene et al, "Prefetching System for a Cache Having a Second Directory for Sequentially Accessed Blocks," U.S. Patent 4,807,110, February 1989.
    • (1989)
    • Pomerene, J.1
  • 19
    • 0003758490 scopus 로고
    • Generalized Correlation Based Hardware Prefetching,
    • Technical Report EE-CEG-95-1, Cornell University, February
    • M. Charney and A. Reeves, "Generalized Correlation Based Hardware Prefetching," Technical Report EE-CEG-95-1, Cornell University, February 1995.
    • (1995)
    • Charney, M.1    Reeves, A.2
  • 30
    • 47349125882 scopus 로고    scopus 로고
    • IBM Unleashes World's Fastest Chip in Powerful New Computer, at http://www-03.ibm.com/press/us/en/pressrelease/21580.wss.
    • "IBM Unleashes World's Fastest Chip in Powerful New Computer", at http://www-03.ibm.com/press/us/en/pressrelease/21580.wss.
  • 32
    • 47349126153 scopus 로고    scopus 로고
    • http://www.micron.com/products/modules/ddr2sdram/fbdimm.html
  • 33
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    • Sun Microsystems. SPARC Architecture Manual V9, 1996.
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  • 34
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    • www.spec.org
  • 38
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    • Accurate Modeling of Aggressive Speculation in Modern Microprocessor Architectures
    • H. Modi, L. Spracklen, Y. Chou, S. Abraham, "Accurate Modeling of Aggressive Speculation in Modern Microprocessor Architectures," in Proceedings of MASCOTS 2005, 2005.
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    • Modi, H.1    Spracklen, L.2    Chou, Y.3    Abraham, S.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.