Reducing DRAM latencies with an integrated memory hierarchy design

IEEE High-Performance Computer Architecture Symposium Proceedings

Volumn , Issue , 2001, Pages 301-312

  Lin, Wei fen ^a   Reinhardt, Steven K ^a   Burger, Doug ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; HIERARCHICAL SYSTEMS; MICROPROCESSOR CHIPS;

CACHE MEMORY; DIRECT RAMBUS CHANNELS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0034818343     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (28)