Correlation prefetching with a user-level memory thread

IEEE Transactions on Parallel and Distributed Systems

Volumn 14, Issue 6, 2003, Pages 563-580

  Solihin, Yan ^a   Lee, Jaejin ^b   Torrellas, Josep ^c  

^a UNIVERSITY OF NORTH CAROLINA   (United States)

^b Seoul National University   (South Korea)

^c University of Illinois at Urbana Champaign   (United States)

Author keywords

Correlation prefetching; Helper threads; Heterogeneous system; Intelligent memory architecture; Memory side prefetching; Prefetching; Processing in memory

Indexed keywords

ALGORITHMS; CACHE MEMORY; COMPUTER SOFTWARE; DATA STRUCTURES; DATA TRANSFER; DYNAMIC RANDOM ACCESS STORAGE; MICROPROCESSOR CHIPS;

CORRELATION PREFETCHING; HELPER THREADS; HETEROGENEOUS SYSTEM; INTELLIGENT MEMORY ARCHITECTURE; MEMORY-SIDE PREFETCHING; PROCESSING-IN MEMORY; USER-LEVEL MEMORY THREAD;

STORAGE ALLOCATION (COMPUTER);

EID: 0042850375     PISSN: 10459219     EISSN: None     Source Type: Journal    
DOI: 10.1109/TPDS.2003.1206504     Document Type: Article

References (36)

1. T. Alexander and G. Kedem, "Distributed Predictive Cache Design for High Performance Memory Systems," Proc. Second Int'l Symp. High-Performance Computer Architecture, pp. 254-263, Feb. 1996.
2. J.L. Baer, "Dynamic Improvements of Locality in Virtual Memory Systems," IEEE Trans. Software Eng., vol. 2, pp. 54-62, Mar. 1976.
3. J.E. Barnes, "Treecode," Inst. for Astronomy, Univ. of Hawaii, ftp://hubble.ifa.hawaii.edu/pub/barnes/treecode, 1994.
4. J.B. Carter, et al. "Impulse: Building a Smarter Memory Controller," Proc. Fifth Int'l Symp. High-Performance Computer Architecture, pp. 70-79, Jan. 1999.
5. R.S. Chappell, J. Stark, S. Kim, S.K. Reinhardt, and Y.N. Patt, "Simultaneous Subordinate Microthreading (SSMT)," Proc. 26th Int'l Symp. Computer Architecture, pp. 186-195, May 1999.
6. M.J. Charney and A.P. Reeves, "Generalized Correlation Based Hardware Prefetching," Technical Report EE-CEG-95-1, Cornell Univ., Feb. 1995.
7. T.F. Chen and J.L. Baer, "Reducing Memory Latency via Non-Blocking and Prefetching Cache," Proc. Fifth Int'l Conf. Architectural Support for Programming Languages and Operating Systems, pp. 51-61, Oct. 1992.
8. S. Choi, D. Kim, and D. Yeung, "Multi-Chain Prefetching: Effective Exploitation of Inter-Chain Memory Parallelism for Pointer-Chasing Codes," Proc. Int'l Conf. Parallel Architectures and Compilation Techniques, pp. 51-61, Sept. 2001.
9. R. Cooksey, D. Colarelli, and D. Grunwald, "Content-Based Prefetching: Initial Results," Proc. Second Workshop Intelligent Memory Systems, pp. 33-55, Nov. 2000.
10. J. Dongarra, V. Eijkhout, and H. van der Vorst, "SparseBench: A Sparse Iterative Benchmark," http://www.netlib.org/benchmark/sparsebench, 2003.
11. M. Dubois and Y.H. Song, "Assisted Execution," CENG Technical Report 98-25, Dept. of Electrical Eng.-Systems, Univ. of Southern California, Oct. 1998.
12. Z. Hu, S. Kaxiras, and M. Martonosi, "Timekeeping in the Memory System: Predicting and Optimizing Memory Behavior," Proc. 29th Int'l Symp. Computer Architecture, May 2002.
13. Z. Hu, M. Martonosi, and S. Kaxiras, "Tag Correlating Prefetchers," Proc. Ninth Int'l Symp. High-Performance Computer Architecture, Feb. 2003.
14. C.J. Hughes, "Prefetching Linked Data Structures in Systems with Merged DRAM-Logic," Master's thesis, Univ. of Illinois at Urbana-Champaign, Technical Report UIUCDCS-R-2001-2221, May 2000.
15. D. Joseph and D. Grunwald, "Prefetching Using Markov Predictors," Proc. 24th Int'l Symp. Computer Architecture, pp. 252-263, June 1997.
16. N. Jouppi, "Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers," Proc. 17th Int'l Symp. Computer Architecture, pp. 364-373, May 1990.
17. M. Karlsson, F. Dahlgren, and P. Stenstrom, "A Prefetching Technique for Irregular Accesses to Linked Data Structures," Proc. Sixth Int'l Symp. High-Performance Computer Architecture, pp. 206-217, Jan. 2000.
18. D. Koufaty and J. Torrellas, "Comparing Data Forwarding and Prefetching for Communication-Induced Misses in Shared-Memory MPs," Proc. Int'l Conf. Supercomputing, pp. 53-60, July 1998.
19. C. Kozyrakis, et al. "Scalable Processors in the Billion-Transistor Era: IRAM," IEEE Computer, pp. 75-78, Sept. 1997.
20. V. Krishnan and J. Torrellas, "A Direct-Execution Framework for Fast and Accurate Simulation of Superscalar Processors," Proc. Int'l Conf. Parallel Architectures and Compilation Techniques, pp. 286-293, Oct. 1998.
21. A. Lai, C. Fide, and B. Falsafi, "Dead-Block Prediction and Dead-Block Correlating Prefetchers," Proc. 28th Int'l Symp. Computer Architecture, pp. 144-154, June 2001.
22. J. Lee, Y. Solihin, and J. Torrellas, "Automatically Mapping Code on an Intelligent Memory Architecture," Proc. Seventh Int'l Symp. High Performance Computer Architecture, Jan. 2001.
23. M.H. Lipasti, W.J. Schmidt, S.R. Kunkel, and R.R. Roediger, "Spaid: Software Prefetching in Pointer and Call Intensive Environments," Proc. 28th Int'l Symp. Microarchitecture, pp. 231-236, Nov. 1995.
24. C. Luk and T.C. Mowry, "Compiler-Based Prefetching for Recursive Data Structures," Proc. Seventh Int'l Conf. Architectural Support for Programming Languages and Operating Systems, pp. 222-233, Oct. 1996.
25. S. Mehrotra, "Data Prefetch Mechanisms for Accelerating Symbolic and Numeric Computation," PhD thesis, Dept. of Computer Science, Univ. of Illinois at Urbana-Champaign, 1996.
26. MIPS, MIPS R10000 Microprocessor User's Manual, Version 2.0, Jan. 1997.
27. NVIDIA, technical brief: NVIDIA nForce Integrated Graphics Processor (IGP) and Dynamic Adaptive Speculative Pre-Processor (DASP), http://www.nvidia.com/, 2002.
28. S. Palacharla and R. Kessler, "Evaluating Stream Buffers as a Secondary Cache Replacement," Proc. 21st Int'l Symp. Computer Architecture, pp. 24-33, Apr. 1994.
29. J. Pomerene, T. Puzak, R. Rechtschaffen, and F. Sparacio, "Prefetching System for a Cache Having a Second Directory for Sequentially Accessed Blocks," US Patent 4,807,110, Feb. 1989.
30. A. Roth, A. Moshovos, and G. Sohi, "Dependence Based Prefetching for Linked Data Structures," Proc. Eighth Int'l Conf. Architectural Support for Programming Languages and Operating Systems, pp. 115-126, Oct. 1998.
31. A. Roth and G. Sohi, "Speculative Data Driven Multithreading," Proc. Seventh Intl. Symp. High-Performance Computer Architecture, Jan. 2001.
32. T. Sherwood, S. Sair, and B. Calder, "Predictor-Directed Stream Buffers," Proc. 33rd Int'l Symp. Microarchitecture, pp. 42-53, Dec. 2000.
33. Y. Solihin, J. Lee, and J. Torrellas, "Using a User-Level Memory Thread for Correlation Prefetching," Proc. 29th Int'l Symp. Computer Architecture, May 2002.
34. Sony Computer Entertainment Inc., http://www.sony.com, 2003.
35. C.-L. Yang and A.R. Lebeck, "Push versus Pull: Data Movement for Linked Data Structures," Proc. Int'l Conf. Supercomputing, pp. 176-186, May 2000.
36. Z. Zhang and J. Torrellas, "Speeding up Irregular Applications in Shared-Memory Multiprocessors: Memory Binding and Group Prefetching," Proc. 22nd Int'l Symp. Computer Architecture, pp. 188-199, June 1995.