6-T SRAM cell design with nanoscale double-gate SOI MOSFETs: Impact of source/drain engineering and circuit topology

Semiconductor Science and Technology

Volumn 23, Issue 7, 2008, Pages

  Rashmi, ^a   Kranti, Abhinav ^a   Armstrong, G Alastair ^a  

^a QUEEN'S UNIVERSITY BELFAST   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK TOPOLOGY; HEALTH; LEAKAGE CURRENTS; MOSFET DEVICES; RANDOM ACCESS STORAGE; TOPOLOGY;

CIRCUIT TOPOLOGIES; DOUBLE GATE (DG); LOW VOLTAGE OPERATIONS; MIXED MODE SIMULATIONS; NANO SCALING; NOISE MARGIN (NM); OPTIMAL DESIGN PARAMETERS; PERFORMANCE METRICS; SOI-MOSFETS; SOURCE/DRAIN (S/D) RESISTANCE; SOURCE/DRAIN ENGINEERING; SRAM CELLS; STATIC NOISE MARGIN (SNM); STATIC RANDOM ACCESS MEMORY (SRAM); SUPPLY-VOLTAGE SCALING;

STATIC RANDOM ACCESS STORAGE;

EID: 47749102120     PISSN: 02681242     EISSN: 13616641     Source Type: Journal    
DOI: 10.1088/0268-1242/23/7/075049     Document Type: Article

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