Design optimization and performance projections of double-gate FinFETs with gate-source/drain underlap for SRAM application

IEEE Transactions on Electron Devices

Volumn 54, Issue 8, 2007, Pages 1934-1942

  Kim, Seung Hwan ^a   Fossum, Jerry G ^b  

^a SAMSUNG Electronics   (South Korea)

^b University of Florida   (United States)

Author keywords

CMOS scalability; Double gate (DG) MOSFETs; Sensitivity to process variations; Threshold voltage control

Indexed keywords

CMOS INTEGRATED CIRCUITS; DESIGN; GATES (TRANSISTOR); OPTIMIZATION; SEMICONDUCTOR DOPING; THRESHOLD VOLTAGE; VOLTAGE CONTROL;

GATE SOURCE/DRAIN (G-S/D) UNDERLAP; PHYSICAL DEVICE/CIRCUIT SIMULATIONS; READ-STATIC NOISE MARGIN;

STATIC RANDOM ACCESS STORAGE;

EID: 34547912102     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2007.901070     Document Type: Article

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