Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2005, Issue , 2005, Pages 398-405

  Tsukamoto, Yasumasa ^a   Nii, Koji ^a   Imaoka, Susumu ^b   Oda, Yuji ^c   Ohbayashi, Shigeki ^a   Yoshizawa, Tomoaki ^a   Makino, Hiroshi ^a   Ishibashi, Koichiro ^a   Shinohara, Hirofumi ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b Renesas Design   (Japan)

^c Sanyo Nyce Corporation   (Japan)

Author keywords

Design form manufacturability (DFM); Local Vth variability; SRAM; Static noise margin

Indexed keywords

CMOS INTEGRATED CIRCUITS; MATHEMATICAL MODELS; RANDOM PROCESSES; SPURIOUS SIGNAL NOISE;

DESIGN FOR MANUFACTURABILITY (DFM); LOCAL VTH VARIABILITY; STATIC NOISE MARGIN;

STATIC RANDOM ACCESS STORAGE;

EID: 33750831908     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2005.1560101     Document Type: Conference Paper

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