Static Noise Margin of the Full DG-CMOS SRAM Cell Using Bulk FinfETs (Omega MOSFETs)

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2003, Pages 27-30

  Park, T ^a,b   Cho, H J ^a   Choe, J D ^a   Han, S Y ^a   Jung, S M ^a   Jeong, J H ^a   Nam, B Y ^a   Kwon, O I ^a   Han, J N ^a   Kang, H S ^a   Chae, M C ^a   Yeo, G S ^a   Lee, S W ^a   Lee, D Y ^a   Park, D ^a   Kim, K ^a   Yoon, E ^b   Lee, J H ^c  

^a SAMSUNG Electronics   (South Korea)

^b Seoul National University   (South Korea)

^c Kyungpook National University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ALUMINUM; CMOS INTEGRATED CIRCUITS; ETCHING; ION IMPLANTATION; LEAKAGE CURRENTS; METALLIZING; MOSFET DEVICES; PHOTOLITHOGRAPHY; SCANNING ELECTRON MICROSCOPY; SILICA; SPURIOUS SIGNAL NOISE; SPUTTERING; THERMOOXIDATION; TRANSMISSION ELECTRON MICROSCOPY;

MICROGRAPH ANALYSIS; SILICIDATION; STATIC NOISE MARGIN;

STATIC RANDOM ACCESS STORAGE;

EID: 0842288297     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. E. J. Nowak et al., IEDM, Tech. Dig., p. 411, 2002..
2. T. Park et al., Symp. on VLSI Tech., Tech. Dig., p. 135, 2003.
3. T. Park et al., DRC, Tech. Dig., p. 33, 2003.
4. S.-M. Jung et al., IEDM, Tech. Dig., p. 419, 2002.