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Volumn 2005, Issue , 2005, Pages 126-127
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High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
a a a a a a a a a a a a a a a a a a a a more.. |
Author keywords
[No Author keywords available]
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Indexed keywords
DUAL STRESS LINER;
SOI TECHNOLOGY;
SRAM CELL;
STRESS NITRIDE LINERS (DSL);
CAPACITANCE;
CMOS INTEGRATED CIRCUITS;
GATES (TRANSISTOR);
MICROPROCESSOR CHIPS;
NITRIDES;
PERFORMANCE;
SILICON ON INSULATOR TECHNOLOGY;
STRESSES;
STATIC RANDOM ACCESS STORAGE;
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EID: 33745148992
PISSN: 07431562
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/.2005.1469238 Document Type: Conference Paper |
Times cited : (67)
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References (3)
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