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Volumn 2005, Issue , 2005, Pages 126-127

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

(82)  Leobandung, E a   Nayakama, H a   Mocuta, D a   Miyamoto, K a   Angyal, M a   Meer, H V a   McStay, K a   Ahsan, I a   Allen, S a   Azuma, A a   Belyansky, M a   Bentum, R V a   Cheng, J a   Chidambarrao, D a   Dirahoui, B a   Fukasawa, M a   Gerhardt, M a   Gribelyuk, M a   Halle, S a   Harifuchi, H a   more..


Author keywords

[No Author keywords available]

Indexed keywords

DUAL STRESS LINER; SOI TECHNOLOGY; SRAM CELL; STRESS NITRIDE LINERS (DSL);

EID: 33745148992     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/.2005.1469238     Document Type: Conference Paper
Times cited : (67)

References (3)


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.