Variability in sub-100nm SRAM designs

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2004, Pages 347-352

  Heald, Raymond ^a   Wang, Ping ^a  

^a SUN MICROSYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CELL TRANSISTORS; SRAM MEMORY CELLS; STATIC NOISE MARGIN (SNM); STATISTICAL VARIATION;

APPROXIMATION THEORY; COMPUTER SIMULATION; CRITICAL PATH ANALYSIS; DATA STORAGE EQUIPMENT; MONTE CARLO METHODS; ROBUSTNESS (CONTROL SYSTEMS); TRANSISTORS;

STATIC RANDOM ACCESS STORAGE;

EID: 16244371339     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (21)

1. E. Seevinck Sr., F. List, J. Lohstroh; "Static-noise margin analysis of MOS SRAM cells," IEEE Journal of Solid-State Circuits, vol. 22, pp. 748-754, Oct. 1987.
2. K. R. Lakshmikumar, R. A. Hadaway, M. A. Copeland, "Characterization and modeling of mismatch in MOS transistors for precision analog design," IEEE Journal of Solid-State Circuits, vol. 21, pp. 1057-1066, Dec. 1986.
3. J. Croon, et. al., "Line Edge Roughness Characterization, Modeling and Impact on Device Behavior," IEDM, Dec. 2002.
4. Semiconductor Industry Association (SIA), International Roadmap for Semiconductors 2001 edition, Austin Tx; International SEMITECH, 2001. Available: http://public.itrs.net.
5. Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu, "New paradigm of predictive MOSFET and interconnect modeling for early circuit design," Proc. of IEEE CICC, pp. 201-204, Jun. 2000.
6. A. Bhavnagarwala, X. Tang, J. Meindl; "The impact of intrinsic device fluctuations on CMOS SRAM cell stability," IEEE Journal of Solid-State Circuits, vol. 36, pp. 658-665, April 2001.
7. A. Hajimiri, R. Heald, "Design Issues in Cross-Coupled Inverter Sense Amplifier," ISCAS Dig. of Technical Papers, May 1998.
8. K. Bowman, B. Austin, J. Eble, X. Tang, J. Meindl; "A physical alpha-power law MOSFET model," IEEE Journal of Solid-State Circuits, vol. 34, pp. 1410-1414, October 1999.
9. K. Bowman, S. Duvall, J. Meindl; "Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration," IEEE Journal of Solid-State Circuits, vol. 37, pp. 183-190, February 2002.
10. K. Bowman, X. Tang, J. Eble, J. Meindl; "Impact of extrinsic and intrinsic parameter fluctuations on CMOS circuit performance," IEEE Journal of Solid-State Circuits, vol. 35, pp. 1186-1193, August 2000.
11. D. Burnett, K. Erington, C. Subramanian, K. Baker; "Implications of fundamental threshold voltage variations for high-density SRAM and logic circuits," Proc. Symp. VLSI Tech., pp. 15-16, June 1994.
12. J. Croon, M. Rosmeulen, S. Decoutere, W. Sansen, H. Maes; "An easy-to-use mismatch model for the MOS transistor," IEEE Journal of Solid-State Circuits, vol. 37, pp. 1056-1064, August 2002.
13. P. Drennan, C. McAndrew; "A comprehensive MOSFET mismatch model," Proc. IEDM, Dec. 1999, pp. 167-170.
14. J. Lohstroh, E. Seevinck, J. de Groot; "Worst-case static noise margin criteria for logic circuits and their mathematical equivalence," IEEE Journal of Solid-State Circuits, vol. 18, pp. 803-807, December 1983.
15. J. Meindl, V. De, D. S. Wills, J. Eble, X. Tang, J. Davis, B. Austin, A. Bhavnagarwala; "The impact of stochastic dopant and interconnect distributions on gigascale integration," IEEE International Solid-State Circuits Conference, vol. XL, pp. 232-233, February 1997.
16. Y. Nakagome, M. Horiguchi, T. Kawahara, K. Itoh, "Review and future prospects of low-power RAM circuits," IBM Journal of Research and Development, vol. 47, no. 5/6, pp. 525-552, September/November 2003.
17. C. Michael, M. Ismail; "Statistical modeling of device mismatch for analog MOS integrated circuits," IEEE Journal of Solid-State Circuits, vol. 27, pp. 154-166, February 1992.
18. P. A. Stolk, F. P. Widdershoven, D. B. M. Klaassen; "Modeling statistical dopant fluctuations in MOS transistors," IEEE Trans. Electron Devices, vol. 45, pp. 1960 -1971, Sept. 1998.
19. X. Tang, V. De, J. D. Meindl; "Intrinsic MOSFET parameter fluctuations due to random dopant placement," IEEE Trans. VLSI Syst., vol. 5, pp. 369-376, Dec. 1997.
20. X. Tang, V. K. De, J. D. Meindl; "MOSFET fluctuation limits on gigascale integration (GSI)," 1998 Eur. Solid-State Device Research Conf. (ESSDERC'98), Bordeaux, France, pp. 508-511, Sept. 1998.
21. S.-C. Wong, K.-H. Pan, D.-J. Ma; "A CMOS mismatch model and scaling effects," IEEE Electron Device Lett., vol. 18, pp. 261-263, June 1997.