FinFET scaling to 10 nm gate length

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2002, Pages 251-254

  Yu, Bin ^a   Chang, Leland ^b   Ahmed, Shibly ^a   Wang, Haihong ^a   Bell, Scott ^a   Yang, Chih Yuh ^a   Tabery, Cyrus ^a   Ho, Chau ^a   Xiang, Qi ^a   King, Tsu Jae ^b   Bokor, Jeffrey ^b   Hu, Chenming ^b   Lin, Ming Ren ^a   Kyser, David ^a  

^a ADVANCED MICRO DEVICES   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; GATES (TRANSISTOR); SEMICONDUCTOR DEVICE MANUFACTURE;

FINFET DEVICES;

MOSFET DEVICES;

EID: 0036923438     PISSN: 01631918     EISSN: None     Source Type: Journal    
DOI: 10.1109/IEDM.2002.1175825     Document Type: Article

References (7)

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3. N. Lindert, Y.-K. Choi, L. Chang, E. Anderson, W.-C. Lee, et al, “Quasi-planar NMOS FinFETs with sub-100nm gate lengths,” Device Research Conference, June 2001, pp.26-27.
4. D.M. Fried, A.P. Johnson, E.J. Nowak, J.H. Rankin, C.R. Willets, “A sub-40nm body thickness n-type FinFET,” Device Research Conference, June 2001, pp. 24-25.
5. Y.-K. Choi, N. Lindert, P. Xuan, S. Tang, D. Ha, E. Anderson, et al, “Sub-20nm CMOS FinFET technologies.” IEDM Tech. Dig., Dec. 2001, pp. 421-424.
6. J. Kedzierski, D.M. Dried, E.J. Nowak, T. Kanarsky, J.H. Rankin, et al, “High-performance symmetric-gate and CMOS-compatible Vt asymmetric-gate FinFET devices,” IEDM Tech. Dig., Dec. 2001, pp. 437-440.
7. F.-L. Yang, H.Y. Chen, F.-C. Chen, Y.-L. Chan, et al, “35nm CMOS FinFETs,” Symp. VLSI Tech., June 2001, pp. 104-105.