Double Raised Source/Drain Transistor with 50 nm Gate Length on 17 nm UTF-SOI for 1.1 μm2 Embedded SRAM Technology

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2003, Pages 31-34

  Oh, Chang Bong ^a   Oh, Myoung Hwan ^a   Kang, Hee Sung ^a   Park, Chang Hyun ^a   Oh, Byung Jun ^a   Kim, Yoon Hae ^a   Rhee, Hwa Sung ^a   Kim, Young Wug ^a   Suh, Kwang Pyuk ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; EPITAXIAL GROWTH; LEAKAGE CURRENTS; MICROELECTRONICS; MOSFET DEVICES; SILICON ON INSULATOR TECHNOLOGY; SPURIOUS SIGNAL NOISE; STATIC RANDOM ACCESS STORAGE; THERMOOXIDATION; TRANSMISSION ELECTRON MICROSCOPY; ULTRATHIN FILMS;

BACK-END OF LINE (BEOL); SELECTIVE EPITAXIAL GROWTH (SEG); STATIC NOISE MARGIN (SNM);

GATES (TRANSISTOR);

EID: 0842309840     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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6. Y. W. Kim et al., IEEE SOI Conf., pp.119, 2002.
7. H.-S. Kang et al., SSDM, pp. 76, 2002.
8. Y.W. Kim et al., Symp. VLSI Tech. Digest, pp.69, 2003.