Dynamic circuit techniques using independently controlled double-gate devices

Proceedings - IEEE International SOI Conference

Volumn 2005, Issue , 2005, Pages 74-76

  Kuang, J B ^a   Kim, K ^b   Chuang, C T ^b   Ngo, H C ^a   Nowka, K J ^a  

^a IBM AUSTIN RESEARCH LABORATORY   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 33744756630     PISSN: 1078621X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOI.2005.1563539     Document Type: Conference Paper

References (6)

1. A. Alvandpour, et al., "A Conditional Keeper Technique for Sub-0. 13μm Wide Dynamic Gates", Dig. Tech. Papers, Symp. VLSI Circuit, 2001, pp. 29-30.
2. C. H. Kim, et al., "A Process Variation Compensating Technique for Sub-90 nm Dynamic Circuits," Dig. Tech. Papers, Symp. VLSI Circuits, 2003, pp. 205-206.
3. M. H. Chiang, et al., "Novel High-Density Low-Power High-Performance Double-Gate Logic Techinques," IEEE Intl SOI Conf., 2004, pp. 122-123.
4. H. Mahmoodi, et al., "High performance and low power domino logic using independent gate control in double-gate SOI MOSFETs," IEEE Intl SOI Conf., 2004, pp. 67-68.
5. K. Kim and J. G. Fossum, "Double-gate CMOS: symmetrical versus asymmetrical gate devices," IEEE Trans. Electron Devices, vol. 48, 2001, pp. 294-299.
6. Taurus-MEDICI, Industry-standard device simulation tool, Mountain View, CA, Synopsis, Inc., 2003.