A low-power Multi-Gate FET CMOS technology with 13.9ps inverter delay, large-scale integrated high performance digital circuits and SRAM

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2007, Pages 106-107

  Von Arnim, K ^a   Augendre, E ^b   Pacha, C ^a   Schulz, T ^a   San, K T ^b,c   Bauer, F ^a   Nackaerts, A ^b   Rooyackers, R ^b   Vandeweyer, T ^b   Degroote, B ^b   Collaert, N ^b   Dixit, A ^b   Singanamalla, R ^b   Xiong, W ^c   Marshall, A ^c   Cleavelin, C R ^c   Schrufer K ^a   Jurczak, M ^b  

^a INFINEON TECHNOLOGIES AG   (Germany)

^b IMEC   (Belgium)

^c TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; DIGITAL ARITHMETIC; DIGITAL CIRCUITS; DIGITAL INTEGRATED CIRCUITS; FIELD EFFECT TRANSISTORS; MESFET DEVICES; METALS; NETWORKS (CIRCUITS); STATIC RANDOM ACCESS STORAGE;

BULK CMOS; CMOS TECHNOLOGIES; CRITICAL PATHS; IN DEPTH ANALYSIS; LARGE-SCALE INTEGRATION (LSI); LOW POWERS; METAL GATES; RING OSCILLATORS; SRAM CELLS; STACK HEIGHT; VLSI TECHNOLOGIES;

TECHNOLOGY;

EID: 39549096358     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2007.4339745     Document Type: Conference Paper

References (13)

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