Fully Working 1.25μm2 6T-SRAM Cell with 45nm Gate Length Triple Gate Transistors

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2003, Pages 23-26

  Yang, Jeong Hwan ^b   Jin, You Seung ^b   Lee, Hyae Ryoung ^b   Rha, Kyoung Seok ^a   Choi, Jung A ^b   Bae, Su Kon ^b   Maeda, Shigenobu ^b   Kim, Young Wug ^b   Suh, Kwang Pyuk ^b  

^a Technology Development Team   (South Korea)

^b SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DATA STORAGE EQUIPMENT; DEPOSITION; ELECTRON MOBILITY; GATES (TRANSISTOR); LEAKAGE CURRENTS; LITHOGRAPHY; MOSFET DEVICES; OXIDATION; POLYSILICON; SILICON WAFERS;

PLANARIZATION; SILICON-ON-INSULATOR (SOI);

STATIC RANDOM ACCESS STORAGE;

EID: 0842309837     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. Fu-Liang Yang et. al., "25 nm CMOS Omega FETs", IEDM 2002, pp.255-258
2. B.Doyle et al., "Tri-Gate Fully-Depleted CMOS Transistors: Fabrication, Design and Layout", VLSI 2003, pp133
3. Robert Chau et al., "Advanced Depicted-Substrate Transistors: Single-gate, Double-gate and Tri-gate(Invited Paper)", SSDM 2002, pp.68-69
4. B.Rainey et al., "Demonstration of FinFET CMOS Circuits" Device Research Conf. 2002, pp47-48
5. E.J.Nowak, "A Functional FinFET-DGCMOS SRAM Cell", IEDM 2002, pp411
6. Yang-Kyu Choi et al., "FinFET Process Refinements for Improved Mobility and Gate Work Function Engineering", IEDM 2002, pp259
7. S.Takagi et al., "On the universality of inversion layer mobility in Si MOSFET's: Part I-Effects of Substrate Impurity Concentration", IEEE Trans. On Elec. Devices, V41 No12 Dec. 1994, pp2357-2368
8. A.Hokazono et al., "14nm Gate Length CMOSFETs Utilizing Low Thermal Budget Process with Poly-SiGe and Ni Salicide", IEDM2002, p.639