Fully-depleted SOI technology using high-K and single-metal gate for 32nm node LSTP applications featuring 0.179μm2 6T-SRAM bitcell

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2007, Pages 267-270

  Fenouillet Beranger, C ^a,d   Denormel, S ^a   Icard, B ^d   Boeuf, F ^a   Coignus, J ^a   Faynot, O ^d   Brevard, L ^d   Buj, C ^d   Soonekindt, C ^b   Todeschini, J ^a   Le Denmat, J C ^a   Loubet, N ^a   Gallon, C ^a   Perreau, P ^d   Manakli, S ^a   Minghetti, B ^a   Pain, L ^d   Arnal, V ^a   Vandooren, A ^c   Aime, D ^c   Tosti, L ^d   Savardi, C ^a   Broekaart, M ^b   Gouraud, P ^a   Leverd, F ^a   Dejonghe, V ^b   Brun, P ^d   Guillermet, M ^d   Aminpur, M ^c   Barnola, S ^d   Rouppert, F ^d   Martin, F ^d   Salvetat, T ^d   Lhostis, S ^a   Laviron, C ^d   Auriac, N ^c   Kornann, T ^b   Chabanne, G ^c   Gaillard, S ^a   Belmont, O ^a   Laffosse, E ^c   Barge, D ^a   Zauner, A ^b   Tarnowka, A ^b   Romanjec, K ^b   Brut, H ^a   Lagha, A ^c   Bonnetier, S ^c   Joly, F ^a   Mayet, N ^c   Cathignol, A ^a   Galpin, D ^a   Pop, D ^a   Delsol, R ^b   Pantel, R ^a   Pionnier, F ^a   Thomas, G ^a   Bensahel, D ^a   Deleonibus, S ^d   Skotnicki, T ^a   Mingam, H ^a   more..

^a STMICROELECTRONICS   (France)

^b NXP SEMICONDUCTORS   (France)

^c FREESCALE SEMICONDUCTOR INC   (United States)

^d CEA LETI   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON DEVICES;

FULLY-DEPLETED; METAL GATES; SOI TECHNOLOGY;

METALS;

EID: 47749097705     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2007.4418919     Document Type: Conference Paper

References (18)

1. F.Boeuf et al., IEDM 2004,
2. S. B. Samavedam et al., IEDM 2002
3. R. Chau et al., in IGIW 2003,
4. S. Yamaguchi et al., VLSI 06
5. P. F. Hsu et al., VLSI 06,
6. http://public.itrs.net,
7. A. Vandooren et al., IEEE Int SOI conf 2005,
8. B. Doris et al., VLSI 05,
9. Y. Yasuda et al., IEDM 2005
10. T. Hoffmann et al., VLSI 06,
11. H. Nakamura et al., VLSI 06,
12. B. Tavel et al., in ESSDERC 2005,
13. F. Boeuf et al., VLSI 05,
14. F. Arnaud et al., VLSI 04,
15. L. Chang et al., VLSI 05,
16. F.L. Yang et al., VLSI 04,
17. D.M. Fried et al., IEDM 04,
18. H.Y. Chen et al., VLSI 05.