Sub-1V, Robust and compact 6T SRAM cell in Double Gate MOS technology

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2007, Pages 2778-2781

  Thomas, Olivier ^a   Reyboz, Marina ^a   Belleville, Marc ^a  

^a MINATEC   (France)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; GATES (TRANSISTOR); MOS DEVICES; VOLTAGE CONTROL;

CELL STABILITY; LOW VOLTAGE APPLICATIONS;

STATIC RANDOM ACCESS STORAGE;

EID: 34548815939     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iscas.2007.378629     Document Type: Conference Paper

References (6)

1. R. V. Joshi et al., "Variability for Sub-100 nm PD/SOI CMOS SRAM Cell, ESSCIRC, pp. 211-214, September 2004.
2. D. Frank, "Monte Carlo simulation of a 30-nm dual-gate MOSFET: How far can silicon go?", IEDM Tech. Dig., pp.553, 1992.
3. C. Mazuré et al., "Advanced SOI substrate Manufacturing", IEEE ICICDT 2004, pp. 105-111
4. M. Reyboz et al., "Explicit Threshold Voltage Based Compact Model of Independent Double Gate MOSFET", WCM 2006.
5. E Seevinck, et. al., "Static-Noise Margin Analysis of MOS SRAM Cells", IEEE JSSC, VOL. SC-22, NO. 5, October 1987.
6. O. Thomas, et. al., "Ultra Low Voltage design considerations of SOI SRAM Memory Cells", ISCAS, VOL. 4, pp. 4049-4097, May 2005.