A 0.314μm2 6T-SRAM cell build with Tall Triple-Gate devices for 45nm node applications using 0.75NA 193nm lithography

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2004, Pages 269-272

  Nackaerts, A ^a   Ercken, M ^a   Demuynck, S ^a   Lauwers, A ^a   Baerts, C ^a   Bender, H ^a   Boulaert, W ^a   Collaert, N ^a   Degroote, B ^a   Delvaux, C ^a   De Marneffe, J F ^a   Dixit, A ^a,b   De Meyer, K ^a,b   Hendrickx, E ^a   Heylen, N ^a   Jaenen, P ^a   Laidler, D ^a   Locorotondo, S ^a   Maenhoudt, M ^a   Moelants, M ^a   Pollentier, I ^a   Ronse, K ^a   Rooyackers, R ^a   Van Aelst, J ^a   Vandenberghe, G ^a   Vandervorst, W ^a   Vandeweyer, T ^c   Vanhaelemeersch, S ^a   Van Hove, M ^a   Van Olmen, J ^a   Verhaegen, S ^a   Versluijs, J ^a   Vrancken, C ^a   Wiaux, V ^a   Jurczak, M ^a   Biesemans, S ^a   more..

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

^c PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ETCHING; LITHOGRAPHY; OPTIMIZATION; SILICON ON INSULATOR TECHNOLOGY; SPURIOUS SIGNAL NOISE; TECHNOLOGY; TUNING; COPPER COMPOUNDS; CYTOLOGY; NICKEL COMPOUNDS; SILICON COMPOUNDS;

CELL LAYOUT; CONTACT HOLES; OPTICAL PROXIMITY CORRECTION (OPC); WAVELENGTHS;

STATIC RANDOM ACCESS STORAGE; CELLS;

193-NM LITHOGRAPHY; 45NM NODE; 6T-SRAM; 6T-SRAMS; FABRICATION PROCESS; GATE-LENGTH; KEY FEATURE; SRAM CELL; STATIC NOISE MARGIN; TALL TRIPLE GATE DEVICES;

EID: 21644472774     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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