Technology and circuit design considerations in quasi-planar double-gate SRAM

IEEE Transactions on Electron Devices

Volumn 53, Issue 2, 2006, Pages 242-250

  Ananthan, Hari ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

Access time; Double gate (DG); FinFET; Leakage; Process variations; Quasi planarity; SRAM; Static noise margin

Indexed keywords

FIELD EFFECT SEMICONDUCTOR DEVICES; GATES (TRANSISTOR); LEAKAGE CURRENTS; OPTIMIZATION; SEMICONDUCTOR DEVICE STRUCTURES; STATIC RANDOM ACCESS STORAGE;

ACCESS TIME; QUASI-PLANAR DOUBLE-GATE; STATIC NOISE MARGIN;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 31744438138     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2005.862697     Document Type: Article

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