Aggressively scaled (0.143 μm 2) 6T-SRAM cell for the 32 nm node and beyond

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2004, Pages 261-264

  Fried, D M ^b   Hergenrother, J M ^a   Topol, A W ^a   Chang, L ^a   Sekaric, L ^a   Sleight, J W ^b   McNab, S J ^a   Newbury, J ^a   Steen, S E ^a   Gibson, G ^a   Zhang, Y ^a   Fuller, N C M ^a   Bucchignano, J ^a   Lavoie, C ^a   Cabral Jr , C ^a   Canaperi, D ^a   Dokumaci, O ^b   Frank, D J ^a   Duch, E A ^a   Babich, I ^a   Wong, K ^b   Ott, J A ^a   Adams, C D ^b   Dalton, T J ^a   Nunes, R ^a   Medeiros, D R ^a   Viswanathan, R ^a   Ketchen, M ^a   Ieong, M ^b   Haensch, W ^a   Guarini, K W ^a   more..

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b Systems and Technology Group   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CELL STABILITY; HIGH-SPEED EMBEDDED MEMORY; SHALLOW TRENCH ISOLATION (STI); STATIC NOISE MARGIN (SNM); 32 NM TECHNOLOGY; 32-NM NODE; 6T-SRAM; 6T-SRAMS; COBALT DISILICIDE; DAMASCENE COPPER INTERCONNECTS; SOI TECHNOLOGY; SRAM CELL; TECHNOLOGY NODES; TRENCH ISOLATION;

CRYSTALLIZATION; ELECTRON BEAM LITHOGRAPHY; LEAKAGE CURRENTS; OPTIMIZATION; SILICON ON INSULATOR TECHNOLOGY; THRESHOLD VOLTAGE; CELLS; CYTOLOGY;

STATIC RANDOM ACCESS STORAGE; PHOTOLITHOGRAPHY;

EID: 21644445541     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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