Fundamental redundancy versus power trade-off in standby SRAM

ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

Volumn 2, Issue , 2007, Pages

  Kumar, A ^a   Qin, H ^a   Ishwar, P ^b   Rabaey, J ^a   Ramchandran, K ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b BOSTON UNIVERSITY   (United States)

Author keywords

Circuit optimization; Error correction coding; Information theory; Memory architecture; Sram chips

Indexed keywords

CIRCUIT OPTIMIZATION; ERROR CORRECTION CODING; MEMORY ARCHITECTURE; SRAM CHIPS;

ELECTRIC NETWORK ANALYSIS; ERROR ANALYSIS; FAULT TOLERANT COMPUTER SYSTEMS; INFORMATION THEORY; MICROPROCESSOR CHIPS; REDUNDANCY; VOLTAGE CONTROL;

STATIC RANDOM ACCESS STORAGE;

EID: 34547529766     PISSN: 15206149     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICASSP.2007.366178     Document Type: Conference Paper

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