Static noise margin variation for sub-threshold SRAM in 65-nm CMOS

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 7, 2006, Pages 1673-1679

  Calhoun, Benton H ^a,b   Chandrakasan, Anantha P ^a,c  

^a IEEE   (United States)

^b University of Virginia   (United States)

^c MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Process variation; SRAM; Static noise margin; Sub threshold; Sub threshold memory; Voltage scaling

Indexed keywords

PROCESS VARIATION; STATIC NOISE MARGIN; SUB-THRESHOLD; SUB-THRESHOLD MEMORY; VOLTAGE SCALING;

DATA STORAGE EQUIPMENT; ELECTRIC POTENTIAL; ENERGY UTILIZATION; SIZE DETERMINATION; THERMAL EFFECTS; THRESHOLD VOLTAGE;

STATIC RANDOM ACCESS STORAGE;

EID: 33746369469     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.873215     Document Type: Conference Paper

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