FinFET SRAM: Optimizing Silicon Fin Thickness and Fin Ratio to Improve Stability at iso Area

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

Volumn , Issue , 2007, Pages 623-626

  Lekshmanan, Dheepa ^a   Bansal, Aditya ^a   Roy, Kaushik ^a  

^a Purdue University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS; MOSFET DEVICES; SILICON; STABILITY;

ACCESS TIME; DEVICE MISMATCH; FIN THICKNESS; MANUFACTURABILITY; PROCESS VARIABILITY; SILICON THICKNESS; THICKNESS VARIATION; WRITE MARGIN;

FINS (HEAT EXCHANGE);

EID: 84938600837     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2007.4405809     Document Type: Conference Paper

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