Controllable inverter delay and suppressing Vth fluctuation technology in silicon on thin BOX featuring dual back-gate bias architecture

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2007, Pages 475-478

  Tsuchiya, Ryuta ^a,b   Ishigaki, Takashi ^b   Morita, Yusuke ^b   Yamaoka, Masanao ^b   Iwamatsu, Toshiaki ^a   Ipposhi, Takashi ^a   Oda, Hidekazu ^a   Sugii, Nobuyuki ^b   Kimura, Shin'ichiro ^b   Itoh, Kiyoo ^b   Inoue, Yasuo ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

NONMETALS; SILICON;

BACK-GATE BIASING; CHANNEL DOPING; SHORT-CHANNEL EFFECT;

ELECTRON DEVICES;

EID: 50249149733     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2007.4418977     Document Type: Conference Paper

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