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Volumn 53, Issue 6, 2006, Pages 1427-1432

Supply and threshold-voltage trends for scaled logic and SRAM MOSFETs

Author keywords

CMOS memory integrated circuits; CMOSFET logic devices; Logic devices; Power consumption; SRAM chips

Indexed keywords

CMOS INTEGRATED CIRCUITS; ENERGY DISSIPATION; ESTIMATION; GATES (TRANSISTOR); HIGH TEMPERATURE OPERATIONS; STATIC RANDOM ACCESS STORAGE; THRESHOLD VOLTAGE;

EID: 33744811444     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2006.874752     Document Type: Article
Times cited : (77)

References (14)
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    • (1997) IEEE Trans. Electron Devices , vol.44 , Issue.11 , pp. 1951-1957
    • Chen, K.1    Hu, C.2    Fang, P.3    Lin, M.R.4    Wollesen, D.L.5
  • 12
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    • "A bitline leakage compensation scheme for low-voltage SRAMs"
    • May
    • K. Agawa, H. Hara, T. Takayanagi, and T. Kuroda, "A bitline leakage compensation scheme for low-voltage SRAMs," IEEE J. Solid-State Circuits, vol. 36, no. 5, pp. 726-734, May 2001.
    • (2001) IEEE J. Solid-State Circuits , vol.36 , Issue.5 , pp. 726-734
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  • 13
    • 0035308547 scopus 로고    scopus 로고
    • "The impact of intrinsic device fluctuations on CMOS SRAM cell stability"
    • Apr
    • A. J. Bhavnagarwala, T. Xinghai, and J. D. Meindl, "The impact of intrinsic device fluctuations on CMOS SRAM cell stability," IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 658-665, Apr. 2001.
    • (2001) IEEE J. Solid-State Circuits , vol.36 , Issue.4 , pp. 658-665
    • Bhavnagarwala, A.J.1    Xinghai, T.2    Meindl, J.D.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.