Exploiting combinatorial redundancy for offset calibration in flash ADCs

IEEE Journal of Solid-State Circuits

Volumn 46, Issue 8, 2011, Pages 1904-1918

  Keskin, Gokce ^a   Proesel, Jonathan ^c   Plouchart, Jean Olivier ^c   Pileggi, Lawrence ^b  

^a INTEL CORPORATION   (United States)

^b CARNEGIE MELLON UNIVERSITY   (United States)

^c IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

ADC; analog to digital converter; calibration; combinatorial redundancy; comparator; flash ADC; statistical element selection

Indexed keywords

ADC; ANALOG-TO-DIGITAL CONVERTER; COMBINATORIAL REDUNDANCY; ELEMENT SELECTION; FLASH-ADC;

ANALOG TO DIGITAL CONVERSION; CALIBRATION; COMPARATORS (OPTICAL); DESIGN; DIGITAL CIRCUITS; SPECIFICATIONS;

REDUNDANCY;

EID: 79960842796     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2011.2157255     Document Type: Conference Paper

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