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Volumn 43, Issue 10, 2008, Pages 2303-2310

A 6-bit 3.5-GS/s 0.9-V 98-mW flash ADC in 90-nm CMOS

Author keywords

A D converter; Active load; ADC; Flash converter; Interpolation; Offset averaging; Overdrive recovery

Indexed keywords

INTERPOLATION; NETWORK PROTOCOLS; SENSOR NETWORKS; SPEED;

EID: 54049119715     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.2004326     Document Type: Conference Paper
Times cited : (68)

References (13)
  • 5
    • 4344690108 scopus 로고    scopus 로고
    • Offset calibrating comparator array for 1.2-V, 6-bit, 4-Gsample/s flash. ADCs using 0.13-μm generic CMOS technology
    • May
    • H. Okada, Y. Hashimoto, K. Sakata, T. Tsukada, and K. Ishibashi, "Offset calibrating comparator array for 1.2-V, 6-bit, 4-Gsample/s flash. ADCs using 0.13-μm generic CMOS technology," in Proc. 29th Eur. Solid-State Circuits Conf., May 2003, pp. 711-714.
    • (2003) Proc. 29th Eur. Solid-State Circuits Conf , pp. 711-714
    • Okada, H.1    Hashimoto, Y.2    Sakata, K.3    Tsukada, T.4    Ishibashi, K.5
  • 8
    • 0035696160 scopus 로고    scopus 로고
    • A 6-b 1.3 Gsample/s A/D converter in 0.35-μm CMOS
    • Dec
    • M. Choi and A. A. Abidi, "A 6-b 1.3 Gsample/s A/D converter in 0.35-μm CMOS," IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1847-1858, Dec. 2001.
    • (2001) IEEE J. Solid-State Circuits , vol.36 , Issue.12 , pp. 1847-1858
    • Choi, M.1    Abidi, A.A.2
  • 10
    • 0033364066 scopus 로고    scopus 로고
    • A 500-Msample/s, 6-bit Nyquist-rate ADC for disk-drive read-channel applications
    • Jul
    • I. Mehr and D. Dalton, "A 500-Msample/s, 6-bit Nyquist-rate ADC for disk-drive read-channel applications," IEEE J. Solid-State Circuits, vol. 34, no. 7, pp. 912-920, Jul. 1999.
    • (1999) IEEE J. Solid-State Circuits , vol.34 , Issue.7 , pp. 912-920
    • Mehr, I.1    Dalton, D.2
  • 11
    • 0036912822 scopus 로고    scopus 로고
    • An embedded 0.8 V/480 μW 6b/22 MHz flash ADC in 0.13-μm digital CMOS process using a nonlinear double interpolation technique
    • Dec
    • J. Lin and B. Haroun, "An embedded 0.8 V/480 μW 6b/22 MHz flash ADC in 0.13-μm digital CMOS process using a nonlinear double interpolation technique," IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1610-1617, Dec. 2002.
    • (2002) IEEE J. Solid-State Circuits , vol.37 , Issue.12 , pp. 1610-1617
    • Lin, J.1    Haroun, B.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.