A 7.6 mW 1.75 GS/s 5 bit flash A/D converter in 90 nm digital CMOS

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2008, Pages 14-15

  Verbruggen, Bob ^a,b   Wambacq, Piet ^a,b   Kuijk, Maarten ^b   Van Der Plas, Geert ^a  

^a IMEC   (Belgium)

^b VRIJE UNIVERSITEIT BRUSSEL   (Belgium)

Author keywords

ADC; Flash; High speed

Indexed keywords

CONSERVATION; EFFICIENCY; MULTICARRIER MODULATION; VLSI CIRCUITS; WIRELESS TELECOMMUNICATION SYSTEMS;

A/D CONVERTERS; ADC; DIGITAL CMOS; FLASH; FLASH-ADC; HIGH SPEED; LOW FREQUENCIES; LOWER-POWER CONSUMPTION; OFFSET CALIBRATION;

ENERGY EFFICIENCY;

EID: 51949083693     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2008.4585933     Document Type: Conference Paper

References (3)

1. G. Van der Plas, S. Decoutere, S. Donnay, "A 0.16pJ/Conversion-Step 2.5mW 1.25GS/s 4b ADC in a 90nm Digital CMOS Process", ISSCC Dig. Tech. Papers, pp. 566-567, Feb. 2006.
2. K. Deguchi, N. Suwa, M. Ito, T. Kumamoto, T. Miki, "A 6-bit 3.5-GS/s 0.9-V 98-mW Flash ADC in 90nm CMOS", Dig. Symp. VLSI Circuits, pp. 64-65, June 2007
3. M. J. M. Pelgrom, A. C. J. Duinmaijer, A.P.G. Welbers, "Matching properties of MOS transistors", IEEE JSSC, vol. 24, pp. 1433-1439, Oct. 1989.