Noise analysis of regenerative comparators for reconfigurable ADC architectures

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 55, Issue 6, 2008, Pages 1441-1454

  Nuzzo, Pierluigi ^a   De Bernardinis, Fernando ^b   Terreni, Pierangelo ^c   Van der Plas, Geert ^a  

^a IMEC   (Belgium)

^b Marvell Semiconductors   (Italy)

^c UNIVERSITY OF PISA   (Italy)

Author keywords

Noise analysis; Reconfigurable analog to digital converter (ADC); Regenerative comparator; Stochastic differential equation

Indexed keywords

COMPARATOR CIRCUITS; COMPARATORS (OPTICAL); DIFFERENTIAL EQUATIONS; MEMORY ARCHITECTURE; RECONFIGURABLE ARCHITECTURES; STOCHASTIC SYSTEMS; TIME DOMAIN ANALYSIS;

COMPARATOR ARCHITECTURE; ELECTRICAL SIMULATION; NOISE ANALYSIS; PROGRAMMABLE ANALOGS; RECONFIGURABLE ANALOG-TO-DIGITAL CONVERTERS; REFERENCE ARCHITECTURE; REGENERATIVE COMPARATOR; STOCHASTIC DIFFERENTIAL EQUATIONS;

ANALOG TO DIGITAL CONVERSION;

EID: 53849089244     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2008.917991     Document Type: Article

References (15)

1. T. Kobayashi, K. Nogami, T. Shirotori, and Y. Fujimoto, "A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architectures," IEEE J. Solid-State Circuits vol. 28, no. 4, pp. 523-527, Apr. 1993.
2. T. B. Cho and P. R. Gray, "A 10 b, 20 Msample/s, 35 mW pipeline A/D converter," IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 166-172, Mar. 1995.
3. P. Nuzzo, G. Van der Plas, F. De Bernardinis, L. Van der Perre, B. Gyselinckx, and P. Terreni, "A 10.6 mW/0.8 pJ power-scalable 1 GS/s 4b ADC in 0.18- μm CMOS with 5.8 GHz ERBW," in Proc. IEEE/ACM Design Autom. Conf. (DAC), Jul. 2006, pp. 873-878.
4. G. Van der Plas, S. Decoutere, and S. Donnay, "A 0.16 pJ/ conversion-step 2.5 mW 1.25 GS/s 4b ADC in a 90-nm digital CMOS process," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2006, pp. 566-567.
5. J. Craninckx and G. Van der Plas, "A 65 fJ/conversion-step, 0-50 MS/s 0-0.7 mW 9 bit charge-sharing SAR ADC in 90-nm digital CMOS," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2007, pp. 246-247.
6. R. Van de Plassche, CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters. Boston, MA: Kluwer Academic, 2003.
7. J. K. Fiorenza, T. Sepke, P. Holloway, C. G. Sodini, and H.-S. Lee, "Comparator-based switched-capacitor circuits for scaled CMOS technologies," IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2658-2668, Dec. 2006.
8. I. E. Opris, "Noise estimation in strobed comparators," Electron. Lett., vol. 33, no. 15, pp. 1273-1274, Jul. 1997.
9. W. Yu and B. H. Leung, "Noise analysis for sampling mixers using stochastic differential equations," IEEE Trans. Circuits Syst. II, Analog Dig. Signal Process., vol. 46, no. 6, pp. 699-704, Jun. 1999.
10. R. Navid, T. Lee, and R. Dutton, "Minimum achievable phase noise of RC oscillators," IEEE J. Solid-State Circuits, vol. 40, no. 3, pp. 630-637, Mar. 2005.
11. B. Oksendal, Stochastic Differential Equations. Berlin, Germany: Springer-Verlag, 1998.
12. B. Wicht, T. Nirschl, and D. Schmitt-Landsiedel, "Yield and speed optimization of a latch-type voltage sense amplifier," IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1148-1158, Jul. 2004.
13. P. Nuzzo, F. De Bernardinis, G. Van der Plas, and P. Terreni, "Efficient calibration through statistical behavioral modeling of a high-speed low-power ADC," in Proc. Ph. D. Res. Microelctron. Electron. (PRIME), Jun. 2006, pp. 297-300.
14. "Affirma Spectre Circuit Simulator Reference," Cadence Design Systems, Inc., Dallas, TX, Jun. 2000.
15. A. Boni, G. Chiorboli, and C. Morandi, "Dynamic characterization of high-speed latching comparators," Electron. Lett., vol. 36, no. 5, pp. 402-403, Mar. 2000.