A CMOS 6-bit 16-GS/s time-interleaved ADC with digital background calibration

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2010, Pages 159-160

  Huang, Chun Cheng ^a   Wang, Chung Yi ^a   Wu, Jieh Tsorng ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

65NM CMOS TECHNOLOGY; DIGITAL BACKGROUND CALIBRATION; FLASH-ADC; OFFSET CALIBRATION; SAMPLING RATES; TIME-INTERLEAVED ADC; TIMING SKEW;

CALIBRATION; CMOS INTEGRATED CIRCUITS;

VLSI CIRCUITS;

EID: 77957750604     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2010.5560312     Document Type: Conference Paper

References (3)

1. C-Y Wang and J-T Wu, "A Multiphase Timing-Skew Calibration Technique Using Zero-Crossing Detection," IEEE Transactions on Circuits and Systems - I: Regular Papers, Vol. 56, No. 6, pp. 1102-1114, June 2009.
2. C-C Huang and J-T Wu, "A Background Comparator Calibration Technique for Flash Analog-to-Digital Converters," IEEE Transactions on Circuits and Systems - I: Regular Papers, Vol. 52, No. 9, pp. 1732-1740, Sept. 2005.
3. G. Van der Plas, S. Decoutere, and S. Donnay, "A 0.16pJ/conversion-step 2.5mW 1.25GS/s 4b ADC in a 90nm Digital CMOS Process," ISSCC Digest of Technical Papers, pp. 2310-2312, Feb. 2006.