Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2009, Pages

  Cheng, K ^a   Khakifirooz, A ^a   Kulkarni, P ^a   Ponoth, S ^a   Kuss, J ^a   Shahrjerdi, D ^b   Edge, L F ^a   Kimball, A ^a   Kanakasabapathy, S ^a   Xiu, K ^a   Schmitz, S ^a   Reznicek, A ^a   Adam, T ^a   He, H ^a   Loubet, N ^c   Holmes, S ^a   Mehta, S ^a   Yang, D ^b   Upham, A ^a   Seo, S C ^a   Herman, J L ^a   Johnson, R ^a   Zhu, Y ^b   Jamison, P ^a   Haran, B S ^a   Zhu, Z ^a   Vanamurth, L H ^a   Fan, S ^a   Horak, D ^a   Bu, H ^a   Oldiges, P J ^b   Sadana, D K ^a   Kozlowski, P ^a   McHerron, D ^a   O'Neill, J ^a   Doris, B ^a   more..

^a IBM RESEARCH   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG DEVICES; CMOS INTEGRATION; DEVICE PERFORMANCE; DRIVE CURRENTS; LOW POWER APPLICATION; LOW-POWER SYSTEMS; MULTIPLE GATES; NEW PROCESS; RAISED SOURCE/DRAIN; SINGLE-MASK; STRESS LINER; THIN SOI;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ELECTRIC POWER SYSTEMS; ELECTRON DEVICES; GATE DIELECTRICS; GATES (TRANSISTOR); MICROPROCESSOR CHIPS;

CMOS INTEGRATED CIRCUITS;

EID: 77952372091     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2009.5424422     Document Type: Conference Paper

References (8)

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6. T. Tomimatsu, et al., Symp. VLSI Tech., 2009, p. 36
7. E. Cartier, et al., Symp. VLSI Tech., 2009, p. 42.
8. O. Weber, et al., IEDM Tech. Dig., 2008, p. 245.