Toward a systematic-variation aware timing methodology

Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 321-326

  Gupta, Puneet ^a   Heng, Fook Luen ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

ACLV; Layout; Lithography; Manufacturability; OPC

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; COMPUTATIONAL GEOMETRY; CONSTRAINT THEORY; IMAGE SENSORS; INFORMATION ANALYSIS; LITHOGRAPHY; PARAMETER ESTIMATION; SILICON WAFERS;

MANUFACTURABILITY; SPATIAL VARIATIONS; STATIC TIMING; TIMING METHODOLOGY;

TIMING CIRCUITS;

EID: 4444353564     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/996566.996660     Document Type: Conference Paper

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