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Volumn , Issue , 2008, Pages 385-388

A 2-gs/s 6-bit flash adc with offset calibration

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK RATE; CMOS PROCESS; CURRENT MODE; DIGITAL OFFSETS; FLASH ANALOG-TO-DIGITAL CONVERTERS; FLASH-ADC; HIGH-SPEED; INPUT FREQUENCY; LOADING DEVICES; OFFSET CALIBRATION; OPERATION MODE; OPERATION SPEED; POWER CONSUMPTION; SAMPLING RATES;

EID: 67649983275     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2008.4708808     Document Type: Conference Paper
Times cited : (10)

References (12)
  • 1
    • 0035696160 scopus 로고    scopus 로고
    • A 6-b 1.3-Gsample/s A/D converter in 0.35-/μm CMOS
    • Dec
    • M. Choi and A. A. Abidi, "A 6-b 1.3-Gsample/s A/D converter in 0.35-/μm CMOS," IEEE J. Solid-State Circuits, vol. 36, pp. 1847-1858, Dec. 2001.
    • (2001) IEEE J. Solid-State Circuits , vol.36 , pp. 1847-1858
    • Choi, M.1    Abidi, A.A.2
  • 2
    • 0036917305 scopus 로고    scopus 로고
    • A 6-b 1.6-Gsample/s flash ADC in 0.18-μmCMOSusing averaging termination
    • Dec
    • P. C. S. Scholtens and M. Vertregt, "A 6-b 1.6-Gsample/s flash ADC in 0.18-μmCMOSusing averaging termination," IEEE J.Solid-State Circuits, vol. 37, pp. 1599-1609, Dec. 2002.
    • (2002) IEEE J.Solid-State Circuits , vol.37 , pp. 1599-1609
    • Scholtens, P.C.S.1    Vertregt, M.2
  • 6
    • 34547154701 scopus 로고    scopus 로고
    • A 0.16pJ/conversion- step 2.5mW 1.25GS/s 4b ADC in a 90nm digital CMOS process
    • Feb
    • G. Van der Plas, S. Decoutere and S. Donnay, "A 0.16pJ/conversion- step 2.5mW 1.25GS/s 4b ADC in a 90nm digital CMOS process," IEEE ISSCC Dig. Tech. Papers, pp. 566-567, Feb. 2006.
    • (2006) IEEE ISSCC Dig. Tech. Papers , pp. 566-567
    • Van der Plas, G.1    Decoutere, S.2    Donnay, S.3
  • 9
    • 22544465883 scopus 로고    scopus 로고
    • A cost-efficient high-speed 12-bit pipeline ADC in 0.18-μm digital CMOS
    • Jul
    • T. N. Andersen et at, "A cost-efficient high-speed 12-bit pipeline ADC in 0.18-μm digital CMOS," IEEE J.Solid-State Circuits, vol.40, pp.1506-1513,Jul. 2005.
    • (2005) IEEE J.Solid-State Circuits , vol.40 , pp. 1506-1513
    • Andersen, T.N.1    et at2
  • 10
    • 84954444951 scopus 로고    scopus 로고
    • A sigma-delta modulation based BIST scheme for A/Dconverters
    • Nov
    • K.-J. Lee, S.-J. Chang and R.-S. Tzeng, "A sigma-delta modulation based BIST scheme for A/Dconverters," IEEE Asian Test Symp., pp. 124-127, Nov. 2003.
    • (2003) IEEE Asian Test Symp , pp. 124-127
    • Lee, K.-J.1    Chang, S.-J.2    Tzeng, R.-S.3
  • 11
    • 0038494530 scopus 로고    scopus 로고
    • A 1.8-V 6-bit 1.3-GHz flash ADC in 0.25 fim CMOS
    • Jul
    • K. Uyttenhove and M. Steyaert, "A 1.8-V 6-bit 1.3-GHz flash ADC in 0.25 fim CMOS," IEEE J. Solid-State Circuits, vol. 38, pp.1115-1122, Jul. 2003.
    • (2003) IEEE J. Solid-State Circuits , vol.38 , pp. 1115-1122
    • Uyttenhove, K.1    Steyaert, M.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.