Co-optimization of circuits, layout and lithography for predictive technology scaling beyond gratings

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 29, Issue 4, 2010, Pages 509-527

  Jhaveri, Tejas ^a   Rovner, Vyacheslav ^b   Liebmann, Lars ^c   Pileggi, Larry ^b   Strojwas, Andrzej J ^b   Hibbeler, Jason D ^d  

^a PDF Solutions   (United States)

^b CARNEGIE MELLON UNIVERSITY   (United States)

^c IBM RESEARCH   (United States)

^d IBM   (United States)

Author keywords

Application specific integrated circuits; Complementary metal oxide semiconductor (CMOS) integrated circuits; Design automation; Design for manufacturability; Integrated circuit economics; Lithography

Indexed keywords

32 NM TECHNOLOGY; CO-OPTIMIZATION; COMPLEMENTARY METAL OXIDE SEMICONDUCTORS; COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) INTEGRATED CIRCUITS; COMPLEX DEVICES; DESIGN AUTOMATION; DESIGN AUTOMATIONS; DESIGN FLOWS; DESIGN RULES; DESIGN-TO-MANUFACTURING; DIGITAL BLOCKS; ENGINEERING SOLUTIONS; FUNCTIONAL DENSITY; INTELLECTUAL PROPERTY CORES; LAYOUT TEMPLATES; LEVEL OF ABSTRACTION; LITHOGRAPHY PROCESS; OPTICAL PROXIMITY CORRECTIONS; POWER DENSITIES; SEMICONDUCTOR INDUSTRY; SYSTEMATIC YIELD; TECHNOLOGY SCALING;

COMPUTER AIDED DESIGN; COST BENEFIT ANALYSIS; DIELECTRIC DEVICES; DIES; INTEGRATED CIRCUITS; LITHOGRAPHY; MACHINE DESIGN; NANOTECHNOLOGY; OPTICAL PROPERTIES; SEMICONDUCTOR DEVICE MANUFACTURE; SILICON WAFERS;

CMOS INTEGRATED CIRCUITS;

EID: 77949888363     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2010.2042882     Document Type: Article

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