A 6-bit, 1.2-gs/s adc with wideband tha in0.13-μmcmos

Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008

Volumn , Issue , 2008, Pages 381-384

  Chen, Bo Wei ^a   Hsien, Szu Kang ^a   Chiang, Cheng Shiang ^a  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS TECHNOLOGY; DATA BANDWIDTH; FLASH-ADC; INPUT CAPACITANCE; ON-CHIP PASSIVES; POWER CONSUMPTION; SOURCE FOLLOWERS; TRACK-AND-HOLD AMPLIFIERS; VOLTAGE BUFFER; WIDE-BAND;

CMOS INTEGRATED CIRCUITS; MULTICARRIER MODULATION;

BROADBAND AMPLIFIERS;

EID: 67649983276     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2008.4708807     Document Type: Conference Paper

References (7)

1. Michael Choi and A. A. Abidi, "A 6b 1.3GSample/s A/D Converter in 0.35-nm CMOS," IEEE ISSCC, pp. 126-127, Feb. 2001.
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3. P. Scholtens and M. Vertregt, "A 6b 1.6GSample/s Flash ADC in 0.18-Hm CMOS using Averaging Termination," IEEE ISSCC, pp. 128-129, Feb. 2002.
4. X. Jiang and M.-C. F. Chang, "A-lGHz Signal bandwidth 6-Bit CMOS ADC with power-efficient averaging," IEEE JSSC, vol. 40, no. 2, pp. 532-535, Feb. 2005.
5. C. Sandner, M. Clara, A. Santner, T. Hartig, and F. Kuttnert, "A 6-Bit 1.2-GS/s Low-Power Flash-ADC in 0.13-nm Digital CMOS," IEEE JSSC, vol. 40, no. 7, pp. 1499-1505, Jul. 2005.
6. Y.-Z. Lin, Y.-T. Liu and S.-J. Chang, "A 5-Bit 4.2GS/s Flash ADC in 0.13-nm CMOS," IEEE CICC, pp. 213-216, Sept. 2007.
7. T. Kobayashi, K. Nogami, T. Shirotori, and Y. Fujimoto, "A Current-Controlled Latch Sense Amplifier and a Static Power Saving Input Buffer for Low-Power Architecture," IEEE JSSC, vol. 28, no. 4, pp. 523-527, Apr. 1993.