A 7.5-GS/s 3.8-ENOB 52-mW flash ADC with clock duty cycle control in 65nm CMOS

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2009, Pages 268-269

  Chung, Hayun ^a   Rylyakov, Alexander ^b   Deniz, Zeynep Toprak ^b   Bulzacchelli, John ^b   Wei, Gu Yeon ^a   Friedman, Daniel ^b  

^a HARVARD UNIVERSITY   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

ADC; Clock duty cycle control; High sampling rate; Low power; Two stage track and hold

Indexed keywords

ADC; ANALOG TO DIGITAL CONVERTERS; BANDWIDTH REQUIREMENT; DUTY CYCLE CONTROL; FLASH-ADC; HIGH SAMPLING RATE; LOW POWER; LOW-POWER CONSUMPTION; NYQUIST FREQUENCY; SAMPLING RATES; TRACK-AND-HOLD; TWO STAGE; TWO-STAGE TRACK AND HOLD;

CLOCKS; VLSI CIRCUITS;

MULTICARRIER MODULATION;

EID: 70449432894     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

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