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Volumn , Issue , 1999, Pages 827-830

NMOS drive current reduction caused by transistor layout and trench isolation induced stress

Author keywords

[No Author keywords available]

Indexed keywords

CARRIER MOBILITY; COMPUTER SIMULATION; ELECTRIC CURRENTS; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; STRESSES;

EID: 0033325124     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (148)

References (10)
  • Reference 정보가 존재하지 않습니다.

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.